Patents by Inventor Hayato OKAMOTO
Hayato OKAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369477Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer inclType: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Applicant: Mitsubishi Electric CorporationInventors: Kakeru OTSUKA, Hayato OKAMOTO, Katsumi NAKAMURA, Koji TANAKA, Koichi NISHI
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Patent number: 11799022Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer inclType: GrantFiled: April 28, 2021Date of Patent: October 24, 2023Assignee: Mitsubishi Electric CorporationInventors: Kakeru Otsuka, Hayato Okamoto, Katsumi Nakamura, Koji Tanaka, Koichi Nishi
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Publication number: 20230299191Abstract: According to the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, in which a cell region, a ballast resistor region, and a termination region surrounding the ballast resistor region are defined, a first insulating film arranged on a front surface of the semiconductor substrate, having a first opening in the cell region, and having at least one second opening in the ballast resistor region, a second insulating film filled in the at least one second opening, a first impurity layer of a second conductivity type arranged on the front surface of the semiconductor substrate below the first opening, and a second impurity layer of the second conductivity type arranged on the front surface of the semiconductor substrate below the at least one second opening, a conductive film arranged from the front surface of the first opening of the semiconductor substrate to the termination region.Type: ApplicationFiled: December 15, 2022Publication date: September 21, 2023Applicant: Mitsubishi Electric CorporationInventors: Yasuhiro YOSHIURA, Eiko OTSUKI, Hayato OKAMOTO
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Publication number: 20230261056Abstract: To suppress an increase in RC-IGBT recovery loss. In a semiconductor device, an IGBT region includes a base layer of a second conductivity type in a surface layer of a drift layer, a diode region includes an anode layer of a second conductivity type in the surface layer of the drift layer, a termination region includes a well layer of the second conductivity type in the surface layer of the drift layer, an impurity concentration profile of the base layer and an impurity concentration profile of the anode layer in a direction along an upper surface of the drift layer cyclically fluctuate, and the impurity concentration profile of the base layer and the impurity concentration profile of the anode layer are different.Type: ApplicationFiled: November 1, 2022Publication date: August 17, 2023Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Yusuke FUKADA, Hayato OKAMOTO
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Patent number: 11444156Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.Type: GrantFiled: April 24, 2020Date of Patent: September 13, 2022Assignee: Mitsubishi Electric CorporationInventors: Hayato Okamoto, Ze Chen
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Publication number: 20220115522Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer inclType: ApplicationFiled: April 28, 2021Publication date: April 14, 2022Applicant: Mitsubishi Electric CorporationInventors: Kakeru OTSUKA, Hayato OKAMOTO, Katsumi NAKAMURA, Koji TANAKA, Koichi NISHI
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Publication number: 20210036107Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region. of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.Type: ApplicationFiled: April 24, 2020Publication date: February 4, 2021Applicant: Mitsubishi Electric CorporationInventors: Hayato OKAMOTO, Ze CHEN