Abstract: A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.

Abstract: A through-hole layout apparatus includes: an extractor extracting an existing through-hole from design data for a semiconductor integrated circuit; a calculator calculating, for each through-hole extracted by the extractor, a layout density of through-holes in a predetermined region; a selector selecting a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor; and a through-hole adder determining, for each target through-hole selected by the selector, a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added.