Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employs 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employes 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch.

Abstract: This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch.

Abstract: An apparatus employing control words to present a synthesized output signal having an output frequency and a delay with respect to an input signal includes: (a) A multiplexer receiving the input signal and having an output and an address input. (b) An output unit generates the output signal in response to a drive signal from the multiplexer. (c) A first register coupled with the multiplexer output. (d) A second register coupled with the multiplexer and the first register. The first register responds to a multiplexer output signal to provide a first control signal to the second register based upon the control words. The second register responds to the multiplexer output signal to provide a second control signal to the address input based upon the first control signal and the control words. The multiplexer presents the drive signal in response to the second control signal.

Abstract: Systems and methods are included for providing anti-aliasing in a sample-and-hold circuit. One embodiment of the present invention includes a method for sampling of an input signal for providing to an analog-to-digital converter. The method comprises generating a sample signal having a given frequency and a period that defines both a sample phase and a hold phase. The method also comprises sampling the input signal at both the sample phase and the hold phase. The method further comprises generating a decimated output sample that is an aggregate of consecutive samples of the input signal obtained during the sample phase and the hold phase.

Abstract: Systems and methods are included for providing anti-aliasing in a sample-and-hold circuit. One embodiment of the present invention includes a method for sampling of an input signal for providing to an analog-to-digital converter. The method comprises generating a sample signal having a given frequency and a period that defines both a sample phase and a hold phase. The method also comprises sampling the input signal at both the sample phase and the hold phase. The method further comprises generating a decimated output sample that is an aggregate of consecutive samples of the input signal obtained during the sample phase and the hold phase.

Abstract: An apparatus employing control words to present a synthesized output signal having an output frequency and a delay with respect to an input signal includes: (a) A multiplexer receiving the input signal and having an output and an address input. (b) An output unit generates the output signal in response to a drive signal from the multiplexer. (c) A first register coupled with the multiplexer output. (d) A second register coupled with the multiplexer and the first register. The first register responds to a multiplexer output signal to provide a first control signal to the second register based upon the control words. The second register responds to the multiplexer output signal to provide a second control signal to the address input based upon the first control signal and the control words. The multiplexer presents the drive signal in response to the second control signal.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: To make use of its full input voltage operating range, an analog-to-digital converter is configured with a switched-capacitor circuit to produce a digital output signal from an analog input signal that lies within a range of input signal voltage. The analog-to-digital converter is configured with an amplifier with a digitally programmable gain and a voltage generator with a digitally controlled output voltage. The voltage generator is coupled through a buffer to the amplifier input and generates an output voltage inversely proportional to the amplifier gain. The amplifier gain and the voltage generator output voltage are controllable with the same digital control signal. The combination of the amplifier and the voltage generator can be configured to produce a voltage for the analog-to-digital converter that lies in a prescribed voltage range, avoiding the need to generate substantial current from the voltage generator for a switched-capacitor circuit.