Abstract: A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

Abstract: A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.

Abstract: A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (?1a . . . (?na) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (?1a . . . ?na), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (?1u . . . ?nu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (?1a . . . ?na) depending on the sampling phases (?1u . . . ?nu) and said adjusting signal (AS).

Abstract: A DSSS system determines transmission reliability of a communication channel in real time. A DSSS transmitter (f0=1/T) generates a Pseudo Noise (PN) code and modulates a carrier source [cos. (2??c)] with a selected chip rate. The transmitter bandwidth is a direct function of the chip rate. The PN coded carrier signal is further modulated by a data signal [m(t)] to provide an output signal [s(t)] to a correlator via a communication channel for purposes of determining the transmission characteristic of the channel. The correlator running a variable length pseudo noise code combines the code and the carrier which relates the incoming data signal to a correlation value for detecting the data signal. The correlation value is compared to a threshold value based upon experience of reliable transmission of data through the communication channel.

Abstract: A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.

Abstract: Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

Abstract: Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.

Abstract: A programmable driver/equalizer with an alterable FIR enables the equalization of serial links or other transmission systems to adapt to a variety of transmission media, specifically, intersymbol interference (ISI). Current mode differential drive circuits are coupled to a transmission media via a Finite Impulse Response (FIR) filter operating in the Z transform mode. The FIR filter includes A and B coefficient setting circuit, and is coupled to the drivers. The driver circuit also includes A coefficient level driver compensation and B coefficient level driver compensation to reduce self-induced ISI from the driver while the filter coefficients are activated. The coefficient setting circuit receive a combination of control bits to select the appropriate response for the driver to the various transmission media parameters. Adjustments to the driver output current are made at data run lengths exceeding certain values and subsequent adjustments are made for data run lengths exceeding larger values.

Abstract: A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

Abstract: A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input.

Abstract: A method and structure for a driver circuit having a plurality of parallel resistors, where a total impedance of all the resistors equals an impedance of an associated transmission line and a switch adapted to combine the resistors to control an output level of the driver. The driver circuit's switch selectively connects the resistors to either a voltage high signal or a voltage low signal. The first set of the switches connect a voltage high signal to a first resistor of the resistors and a second set of switches connect a voltage low signal to a second resistor of the resistors. The switch has a matched pair of opposite type transistors. The driver circuit has balancing resistors connected to the switch, the balancing resistors are sized to balance the resistance within the driver circuit. The resistors are the balancing resistors and the drivers are connected to the switches.

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Abstract: A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains.

Abstract: A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.

Abstract: A voltage generating system provides a plurality of different voltages for powering a dynamic nonvolatile random access memory (NVRAM) chip. The voltage generating system includes a pair of charge pumps. Each charge pump is coupled to a controller that senses the voltage level at the output of the charge pump and generates an enabling signal when said voltage is at a predetermined value. The signal activates a power down circuit which adjusts the charge pump output to a desired voltage level. A programmable oscillator provides the clocking signals for the controller. The charge pumps and programmable oscillators are periodically deactivated. As a result, the overall power consumption of the chip is reduced.

Abstract: A programmable oscillator is provided for use on an integrated circuit chip. The oscillator includes a plurality of inverter delay stages connected in tandem between an input and an output node. A single FET device couples a node common to all of the inverter delay stages to a ground potential. Another FET device controls the input node. When a logic enabling signal is appropriately applied to the FET devices, the oscillator is controlled so that internal nodes of the oscillator float high when it is off and no energy is dissipated. In addition, the amount of delays between the delay stages and the input stage of the load is such that the load supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load.

Abstract: High voltage tolerant FET circuits are characterized by the use of shield structures surrounding source/drain diffusion pockets, with the shields tied to apropriate potentials, which in some cases is the associated gate potential. Some embodiments use enhancement mode devices which however have implanted channels underlying the shield structures. Operation of several embodiments is achieved near the snap-back limits by the use of a clamp to maintain potential drop below this limit. High voltage switching at heavy loads is achieved by a voltage divider providing appropriate gate potentials to the load carrying FETs.

Abstract: A reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate having improved capacitive coupling to the floating gate through a thin oxide grown on single crystal silicon.