Patents by Inventor Hayden Clavie Cranford
Hayden Clavie Cranford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9281810Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.Type: GrantFiled: May 13, 2014Date of Patent: March 8, 2016Assignee: QUALCOMM IncorporatedInventors: Guneet Singh, Hayden Clavie Cranford, Jr., Michael Thomas Fertsch
-
Publication number: 20150333743Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Inventors: Guneet Singh, Hayden Clavie Cranford, JR., Michael Thomas Fertsch
-
Patent number: 8130887Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.Type: GrantFiled: May 20, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Martin Leo Schmatz, Karl David Selander, Michael Anthony Sorna
-
Patent number: 8054926Abstract: The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.Type: GrantFiled: May 6, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Martin L. Schmatz, Thomas H. Toifl
-
Patent number: 7893766Abstract: A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.Type: GrantFiled: September 10, 2009Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Todd Morgan Rasmus, Joseph Marsh Stevens
-
Patent number: 7692447Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.Type: GrantFiled: May 6, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Christian I. Menolfi, Martin Leo Schmatz, Thomas H. Toifl
-
Patent number: 7684517Abstract: Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.Type: GrantFiled: March 10, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Westerfield John Ficken
-
Patent number: 7646839Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.Type: GrantFiled: October 13, 2005Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Vernon Roberts Norman, Martin Leo Schmatz
-
Patent number: 7567614Abstract: A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.Type: GrantFiled: June 10, 2008Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Juan Antonio Carballo, Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Brian Joel Schuh
-
Patent number: 7522687Abstract: The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).Type: GrantFiled: August 29, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Martin L. Schmatz, Thomas H. Toifl
-
Publication number: 20090091375Abstract: A system is disclosed. The system includes a first circuit, the first circuit includes a bias device for allowing the first circuit to transition between a first mode and a second mode. The system further includes a second circuit which controls the bias device. The second circuit provides a bias voltage at a sub-threshold voltage level to the bias device when the first device is in one of the first and the second mode. The second circuit provides a bias voltage at a threshold voltage level or higher when the first device is in one of the first and the second mode. Accordingly, the transition time between modes of the first circuit is minimized.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carrie Ellen COX, Hayden Clavie CRANFORD, JR., Todd Morgan RASMUS, Steven Mark CLEMENTS
-
Patent number: 7471101Abstract: Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration.Type: GrantFiled: November 19, 2007Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Louis Lu-Chen Hsu, James Stephen Mason, Chih-Chao Yang
-
Publication number: 20080285695Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.Type: ApplicationFiled: May 20, 2008Publication date: November 20, 2008Inventors: Hayden Clavie Cranford, JR., Gareth John Nicholls, Vernon Roberts Norman, Martin Leo Schmatz, Karl David Selander, Michael Anthony Sorna
-
Publication number: 20080284466Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.Type: ApplicationFiled: May 6, 2008Publication date: November 20, 2008Inventors: Hayden Clavie Cranford, JR., Christian I. Menolfi, Martin Leo Schmatz, Thomas H. Toifl
-
Publication number: 20080232530Abstract: A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.Type: ApplicationFiled: June 10, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Juan Antonio Carballo, Hayden Clavie Cranford, Gareth John Nicholls, Vernon Roberts Norman, Brian Joel Schuh
-
Publication number: 20080217614Abstract: Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration.Type: ApplicationFiled: May 21, 2008Publication date: September 11, 2008Inventors: Hayden Clavie Cranford, Louis Lu-Chen Hsu, James Stephen Mason, Chih-Chao Yang
-
Patent number: 7418032Abstract: A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.Type: GrantFiled: March 15, 2005Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Juan Antonio Carballo, Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Brian Joel Schuh
-
Patent number: 7408374Abstract: Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration.Type: GrantFiled: December 5, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Louis Lu-Chen Hsu, James Stephen Mason, Chih-Chao Yang
-
Patent number: 7406135Abstract: Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.Type: GrantFiled: June 22, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Hayden Clavie Cranford, Jr., Westerfield John Ficken
-
Publication number: 20080165897Abstract: Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.Type: ApplicationFiled: March 10, 2008Publication date: July 10, 2008Inventors: Hayden Clavie Cranford, Westerfield John Ficken