Abstract: A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.

Abstract: Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

Abstract: The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and accuracy of the recovery are optimized without centering of oversampling. Further, random errors due to edge mis-tracking are minimized. The receiver utilizes a phase rotator to detect the edge position of the bits of the data stream, select the optimum data sample and generate early and late signals if the detected edge is not in the expected position. A phase locked loop provides a frequency source for the phase rotator. At least three evenly spaced samples are detected for each bit. A sample processing algorithm, preferably an adaptive behavior algorithm, is used for centering the bit edge between two of the samples.

Abstract: A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

Abstract: In an electronic system such as a communications integrated circuit including a plurality of components, e.g., transmitters, each of which are operative to demand current responsive to a control signal applied thereto, an apparatus for time-distributing current demand comprises a first phase control circuit configured to receive a reference clock signal and operative to generate a synchronized output signal therefrom, the first phase control circuit generating a phase control signal for synchronizing the output signal to the reference clock signal. A plurality of second phase control circuits is responsive to at least one input control signal and to the phase control signal and operative to apply a plurality of phased output control signals to the plurality of components, the phased output control signals phased with respect to one another by time intervals that are dependent upon the phase control signal.

Abstract: An adaptive interface and method of operation facilitate connection of a work station in a Local Area Network (LAN) using Shielded Twisted Pair (STP) cabling to an Ethernet 10/100BASE TX installation using Unshielded Twisted Pair (UTP). The work station is coupled through the adaptive interface to the STP cabling system emulating a given number of meters of UTP cabling. The interface adapter comprises at one end a RJ 45 connector adapted for connection to the STP cabling and at the other end a MIC_S token ring connector coupled to an Ethernet adapter through the STP cabling system. The adaptive interface includes programmatically controlled filters interconnecting the RJ 45 and MIC_S connectors. The filter comprises a series of 1 . . . N switchable lumped passive element units which can be sequentially connected into the STP cabling to emulate the amplitude attenuation and phase shift of a preselected length of UTP 5 cabling, typically in the range of 20 meters.

Abstract: A CMOS device fabricated in a silicon-on-insulator structure and including circuitry and methods in a first embodiment dynamically shifts the threshold voltage of the CMOS device in a receiver to provide improved noise margin and in a second embodiment dynamically matches the threshold voltages in a differential amplifier to correct for manufacturing offset. To dynamically shift the threshold voltage for noise immunity, the back gate or bulk nodes of the devices is shifted through two similar circuits comprised of npn inverters with clamping devices. The back gate of the n device is biased at 0 volts for the maximum Vth and is biased at +1 threshold for the minimum Vth of the device. Only the back gate of the p device is biased at Vdd for the maximum Vth of the device and is biased at 1 Vth below Vdd for the minimum Vth of the device. The Vth of the n device and the p device should be less than the forward bias of the respective source volt junctions to prevent unwanted bipolar currents.

Abstract: A network driver includes first and second driver circuits and a controller which controls the driver circuits. The first driver circuit is coupled to a first node, and the first driver circuit sources first and second discrete currents to the first node and sinks first and second discrete currents from the node. The second driver circuit is coupled to a second node, and the second driver circuit sources the first and second discrete currents to the second node and sinks the first and second discrete currents from the second node. The controller controls the driver circuits so that the first driver circuit sources and the second driver circuit sinks the first current followed by the second current and so that the first driver circuit sinks and the second driver circuit sources the first current followed by the second current. Related methods are also discussed.

Abstract: An integrated D/A converter has a first feedback circuit for generating a first bias voltage to compensate for systemic changes. A second feedback circuit includes a plurality of switchable current sources biased by the first bias voltage and controlled by an externally supplied attenuation control signal to generate a second bias voltage which is applied to control the D/A current sources.

Abstract: A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.

Abstract: The disclosed circuit is to provide a current source for use on a semiconductor chip having field effect transistors (FET) deposited therein to compensate for variations in the substrate voltage source. Analog type circuits when alone on a semiconductor chip or combined with digital type logic circuits are normally susceptible to disturbances in the bias voltage applied to the substrate of the chip. The obtaining of a uniform output response from an analog type circuit due to an input voltage change has heretofore required the use of off-chip precision voltage sources. Such expensive precision sources can be eliminated and normally variable (.+-. 15%) supplies can be used by providing an on-chip compensating current source which combines with other circuits to provide stable reference voltage levels on the chip for use by the analog circuits.