Abstract: A plant watering apparatus has a container (1) filled with a suitable growth medium (2) and is attached to a foliage support plate (3) by a bar (4) operatively coupled with a spring loaded water control valve (6). Decreasing weight of the container opens the valve to feed water to container. The plate (3) is supported by a wall or ceiling bracket (10) by means of suspension rods (11). Plants (12) are added through holes (14) in the plate (3) and the plant root ball (13) is embedded within the medium (2) with the plant foliage overlying the plate (3). When sufficient water is present in the container 1 the spring loaded valve 6 will be closed. As the medium (2) in the container dries out the weight will reduce and the valve will commence opening. The foliage is supported by the plate (3) and foliage growth will not significantly add to the weight of the container and thus will not affect the operating point of the valve over extended periods of time.

Abstract: Methods and systems for inventory management are disclosed. In one embodiment, an inventory manager may use an inventory management system to perform an inventory management process. The inventory management process includes generating inventory data points simulating a demand and a supply chain response time and providing an inventory diagram based on the simulated demand and supply chain response time. The inventory management process further includes determining a variability inventory level corresponding to a service level based on the inventory diagram and providing a proper inventory level based on the variability inventory level.

Abstract: Methods and systems for inventory management are disclosed. In one embodiment, an inventory manager may use an inventory management system to perform an inventory management process. The inventory management process includes receiving inventory management data related to a service level, a supply chain response time, and demand, and determining a base inventory based on the supply chain response time the demand. The inventory management process further includes determining a variability inventory based on one or more variations in the supply chain response time and the demand and the service level, and providing a proper inventory level based on consideration of the base inventory and the variability inventory.

Abstract: A pixel cell array of a light valve does not rely upon photolithography to define inter-pixel spacing. Instead, adjacent pixels of the array are electronically insulated from one another by spacers formed by etching a dielectric layer conforming to sidewalls of a patterned sacrificial layer. Removal of the sacrificial layer, followed by formation of a metal layer over the dielectric spacer structures and chemical-mechanical polishing of the metal layer, completes fabrication of the array. The thickness of the spacer sidewalls, and hence inter-pixel spacing, is determined by the rate of formation of the conforming dielectric layer. This rate can be precisely controlled to produce spacer structures having a thickness of less than the minimum linewidth of a given photolithography system. In this manner, pixel arrays having significantly reduced inter-pixel spacing and correspondingly higher cell densities can be created.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A light valve array features discrete pixel cells electronically isolated by dielectric spacers formed by etching a dielectric layer conforming to sidewalls of a patterned first metal layer. Formation of a second metal layer over the dielectric spacer structures, followed by chemical-mechanical polishing of the second metal layer to stop on the tips of the sidewall spacers, completes fabrication of the array. Interpixel regions corresponding to the dielectric spacers are substantially shielded from incident light by projecting metal edges of the electrodes supported by the curved upper surface of the spacer structures.

Abstract: A light valve array features discrete pixel cells electronically isolated by dielectric spacers formed by etching a dielectric layer conforming to sidewalls of a patterned sacrificial layer. The sacrificial layer is then removed selective to the dielectric spacer structures. A metal layer is formed over the dielectric spacer structures. Chemical-mechanical polishing of the metal layer to stop on the tips of the sidewall spacers completes fabrication of the array. Interpixel regions corresponding to the dielectric spacers are substantially shielded from incident light by projecting electrode edges formed over the curved upper surface of the spacer structures.

Abstract: A pixel cell array of a light valve does not rely upon photolithography to define inter-pixel spacing. Instead, adjacent pixels of the array are electronically insulated from one another by spacers formed by etching a dielectric layer conforming to sidewalls of a patterned first metal layer. Formation of a second metal layer over the dielectric spacer structures, followed by chemical-mechanical polishing of the second metal layer to reveal the tops of the sidewall spacers, completes fabrication of the array. The thickness of the spacer sidewalls, and hence inter-pixel spacing, is determined by the rate of formation of the conforming dielectric layer. This rate can be precisely controlled to produce spacer structures having a thickness less than the minimum linewidth of a given photolithography system. In this manner, pixel arrays having greatly reduced inter-pixel spacing and correspondingly higher cell densities can be created.

Abstract: A pixel cell array of a light valve does not rely upon photolithography to define inter-pixel spacing. Instead, adjacent pixels of the array are electronically insulated from one another by spacers formed by etching a dielectric layer conforming to sidewalls of a patterned sacrificial layer. Removal of the sacrificial layer, followed by formation of a metal layer over the dielectric spacer structures and chemical-mechanical polishing of the metal layer, completes fabrication of the array. The thickness of the spacer sidewalls, and hence inter-pixel spacing, is determined by the rate of formation of the conforming dielectric layer. This rate can be precisely controlled to produce spacer structures having a thickness of less than the minimum linewidth of a given photolithography system. In this manner, pixel arrays having significantly reduced inter-pixel spacing and correspondingly higher cell densities can be created.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A DMOS structure is formed with P-body and N-source implantations are self-aligned using the same photoresist mask. Following formation of field isolation structures and removal of the composite nitride, a `double-implantation` of P body and N source is made using a single resist masking stage. This process flow utilizes a relatively low N-source implantation dose, as N-source and P-body implantations are subsequently thermally diffused together (co-driven) using the original thermal budget of the P-body drive-in. The N-source implant thus now sees the same thermal budget as does the P-body implant. As a result in this process scheme, overetching of P-body and N-source during composite nitride removal is eliminated, while process simplicity is conserved. Moreover, channel overlap remains self-aligned by implanting N-source and P-body through the same mask. Differing rates of thermal diffusion of the P and N type dopant determine the extent of channel overlap.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A lamp reflector comprises a dished body having a front opening and a rear aperture for a bulb having a filament. The dished body has an upper paraboloid reflective surface subtending an angle of about 165.degree. at the optical axis. The body also has a lower paraboloidal reflective surface whose optical axis is coincident with. The filament lies on axis. The filament lies in front of the focus of the upper reflective portion but behind the focus of the lower reflective portion. The reflective portions and define an upwardly inclined step portion and a horizontally disposed step portion.