Abstract: A method and apparatus for generating a multiport static random-access memory (SRAM) in an integrated circuit. The apparatus includes a tape drive for accepting parameters describing a particular technology process and a keyboard for accepting user specifications of a desired multiport RAM. The user specifications include the number of words the RAM is capable of storing, the number of bits comprising each word, the number of READ ports, and the number of WRITE ports. The apparatus includes a computer which has been programmed to automatically generate the layout of a RAM including a central memory array core, READ and WRITE address buffers and decoders, data input and output buffers, and sense amplifiers. In order to reduce the area covered by the RAM, the READ and WRITE address ports are generally positioned on opposite sides of the memory array core, but so that the number of ports on the opposite sides are as nearly equal as possible.