Abstract: A low-jitter digital clock signal generating system which uses optical pulses output from a pulse laser includes a first balanced photodetector that converts first and second optical pulses with a delayed time interval into first and second electrical pulses through first and second photodiodes and outputs first and second modulated pulses generated by allowing the first and second electrical pulses to partially overlap each other, a second balanced photodetector that converts third and fourth optical pulses with the delayed time interval into third and fourth electrical pulses through third and fourth photodiodes, and outputs a second modulated pulse generated by allowing the third and fourth electrical pulses to partially overlap each other, and a capacitor. The capacitor is charged by the first modulated pulse, is discharged by the second modulated pulse, and outputs a voltage according to the charging and discharging as a clock signal.

Abstract: Disclosed is a semiconductor device and a clock system including a pulse laser-based clock distribution network. The semiconductor device includes a current pulse generator that generates a current pulse train based on a first optical pulse train and a second optical pulse train, a clock distribution network that outputs a clock based on the current pulse train, a CDN detector that detects at least one of status information of the clock distribution network and the output clock to generate detection information, and control logic that generates a control signal for regulating a current of the current pulse train based on the detection information.

Abstract: Disclosed is a stochastic time-to-digital converter, which includes a first arbiter cell that compares a timing of a reference signal and a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and outputs a first comparison result, a second arbiter cell that compares the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and outputs a second comparison result, and a binary converter that calculates a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.

Abstract: Disclosed is a stochastic time-to-digital converter, which includes a first arbiter cell that compares a timing of a reference signal and a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and outputs a first comparison result, a second arbiter cell that compares the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and outputs a second comparison result, and a binary converter that calculates a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.

Abstract: Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

Abstract: Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

Abstract: Provided is a digital equalizer which outputs a decision value corresponding to reception data transmitted from a data transmitter and is located in a data receiver. The digital equalizer includes at least one flip-flop which stores an adjacent bit sequence which is previous computing information; and a computing device which receives an output value of an analog to digital converter as a first input value, receives the adjacent bit sequence as a second input value, and outputs the decision value which is a binary value of the first input value by referring to a lookup table with respect to the first input value and the second input value.