Patents by Inventor Hazara Singh Rathore
Hazara Singh Rathore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9287186Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: GrantFiled: May 28, 2008Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Publication number: 20080224135Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: ApplicationFiled: May 28, 2008Publication date: September 18, 2008Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang, Conal Eugene Murray
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Patent number: 7388224Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: GrantFiled: August 10, 2006Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 7345305Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.Type: GrantFiled: October 12, 2005Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Lynne Marie Gignac, Vincent J. McGahay, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 7279411Abstract: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.Type: GrantFiled: November 15, 2005Date of Patent: October 9, 2007Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Du Binh Nguyen, Hazara Singh Rathore
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Patent number: 7163883Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: October 27, 2003Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Patent number: 7098054Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: GrantFiled: February 20, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 6989282Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.Type: GrantFiled: April 1, 2004Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Lynne Marie Gignac, Vincent J. McGahay, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 6734090Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: GrantFiled: February 20, 2002Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20040087078Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: October 27, 2003Publication date: May 6, 2004Inventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Publication number: 20030157794Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.Type: ApplicationFiled: February 20, 2002Publication date: August 21, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra N. Agarwala, Hormazdyar Minocher Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Binh Nguyen, Richard W. Procter, Hazara Singh Rathore, Chunyan E. Tian, Brett H. Engel
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Patent number: 5976970Abstract: A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang.Type: GrantFiled: March 29, 1996Date of Patent: November 2, 1999Assignee: International Business Machines CorporationInventors: Hormazdyar Minocher Dalal, Hazara Singh Rathore
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Patent number: 5760595Abstract: A test socket is provided as part of a high temperature electromigration test system to allow the prediction of median time to failure to temperatures in excess of 450.degree. C. of VSLI interconnects.Type: GrantFiled: September 19, 1996Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Robert Daniel Edwards, Du Binh Nguyen, James Joseph Poulin, Hazara Singh Rathore, Richard George Smith