Patents by Inventor Hazel Schofield

Hazel Schofield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070096316
    Abstract: A flip chip Schottky die is provided, which includes three contact bumps extending from a top surface of the die for electrically connecting with a board, a first and second bump being cathode contacts, and a third bump being an anode contact and having a larger surface than each of the first and second bumps for a 0.5 ampere device. Each bump is substantially rectangular at its base, but may have a curved or arched top surface on a square die. Also, provided is a contact bump useful in a flip chip device, such as a MOSFET or diode for a current of 1.0 amperes that includes a solder body of PbSn or a solder body free of lead comprising SnAgCu. Such a contact bump is substantially rectangular, and a height of approximately 120 ?m.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 3, 2007
    Inventors: Hazel Schofield, Slawomir Skocki, Philip Adamson
  • Publication number: 20060261473
    Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.
    Type: Application
    Filed: April 24, 2006
    Publication date: November 23, 2006
    Inventors: Norman Connah, Mark Pavier, Phillip Adamson, Hazel Schofield
  • Publication number: 20060220123
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Application
    Filed: June 5, 2006
    Publication date: October 5, 2006
    Inventors: Martin Standing, Hazel Schofield
  • Publication number: 20050186707
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
    Type: Application
    Filed: April 27, 2005
    Publication date: August 25, 2005
    Inventors: Martin Standing, Hazel Schofield