Abstract: The visualization of a storage access on a timeline that represents various disk access events, such as a storage read event, or a storage write event. The storage access timeline may be formulated using event data gathered regarding storage access events, such as storage read requests, or storage write requests. The timeline may be displayed in conjunction with non-storage events, such as thread events, process events, processor events, or such, in order to give a visual indication of what is causing the storage access events. There may even be a control for displaying an identification of the file being accessed for one or more of the storage access events. With a better understanding of correlation between storage access events and application operation, optimization of the application itself may be achieved to more efficiently interface with the storage medium.

Abstract: The present invention extends to methods, systems, and computer program products for time-based navigation within resource utilization data. A computer system is configured to present resource utilization data representing performance of computer resources. The resource utilization data is displayed on a diagnostic data trace during the execution of the application. The user can select a desired time range and the resource utilization data within the time range will be displayed at other traces. The diagnostic data trace is still presented so that the user can understand the relation between the selected time range and the overall time length. Further, the user can modify the selected time range by change the extents of the selected time range using resizing tool. The resource utilization data within the modified selected time range, similarly, is also displayed along with the diagnostic data trace.

Abstract: The present invention extends to methods, systems, and computer program products for time-based navigation within resource utilization data. A computer system is configured to present resource utilization data representing performance of computer resources. The resource utilization data is displayed on a diagnostic data trace during the execution of the application. The user can select a desired time range and the resource utilization data within the time range will be displayed at other traces. The diagnostic data trace is still presented so that the user can understand the relation between the selected time range and the overall time length. Further, the user can modify the selected time range by change the extents of the selected time range using resizing tool. The resource utilization data within the modified selected time range, similarly, is also displayed along with the diagnostic data trace.

Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.

Abstract: A thread execution analyzer analyzes blocking events of threads in a program using execution data and callstacks collected at the blocking events. The thread execution analyzer attempts to identify an application programming interface (API) responsible for each blocking event and provides blocking analysis information to a user. The blocking analysis information may be used by a developer of the program to understand the causes of blocking events that occur for threads of the program.

Abstract: Normalizing time across machines in a distributed system. A method includes obtaining one or more points defining differences in time between machines in the distributed system. Using the points, a determination of one or more time measurement drifts between machines is made. The one or more time measurement drifts indicate changing differences in time over time. One or more traces are collected. Each trace includes one or more events. Each event is correlated to a time stamp from one of the machines in the distributed system. Using the one or more determined time measurement drifts, the time stamps are normalized.

Abstract: A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data.

Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: An analysis and visualization depicts how an application is leveraging processor cores of a distributed computing system, such as a computer cluster, in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime and the amount of overhead used by libraries or middleware. Information regarding processes or threads running on the nodes over time is received, analyzed, and presented to indicate portions of computer cluster that are used by the application, idle, other processes, and libraries in the system. The analysis and visualization can help a developer understand or confirm contention for or under-utilization of system resources for the application and libraries.

Abstract: A dynamic shared-memory data race detection tool with data-scoping capabilities to reduce runtime overheads is disclosed. The tool allows users to restrict analysis of memory locations to heap and/or stack variables that are of interest to them using explicit calls to functions provided in a library that is part of the race detection tool. The application code is instrumented to insert probes at all memory instructions and linked with the data race detection library to perform data-scoped race detection.

Abstract: The present invention extends to methods, systems, and computer program products for indicating parallel operations with user-visible events. Event markers can be used to indicate an abstracted outer layer of execution as well as expose internal specifics of parallel processing systems, including systems that provide data parallelism. Event markers can be used to show a variety of execution characteristics including higher-level markers to indicate the beginning and end of an execution program (e.g., a query). Inside the execution program (query) individual fork/join operations can be indicated with sub-levels of markers to expose their operations. Additional decisions made by an execution engine, such as, for example, when elements initially yield, when queries overlap or nest, when the query is cancelled, when the query bails to sequential operation, when premature merging or re-partitioning are needed can also be exposed.

Abstract: A method of providing a visualization of states of a process includes identifying a set of potential states that can occur during the process and a corresponding set of colors, with each color in the set of colors corresponding to one of the potential states. A fixed ordering is established for the set of colors. A timeline graph including a plurality of colored vertical bars is displayed. Each colored vertical bar corresponds to a time interval of the process and includes at least one color selected from the set of colors based on at least one state occurring during the time interval corresponding to the vertical bar. The plurality of colored vertical bars includes a set of multiple-color vertical bars that each include a plurality of colors appearing in a vertical order based on the fixed ordering.

Abstract: Program profile data is used to prepare temporal cost-incurrence fingerprints, which show when a given method or method frame incurred specified cost(s) during a period of interest while a program was/is executing. Relationships between methods can be elicited by studying their temporal cost-incurrence fingerprints. Methods which are often good candidates for optimization can be automatically selected by identifying a small set of methods whose amount of cost lies within specified bounds relative to the most costly method, or in absolute terms, and whose respective fingerprints differ from one another.

Abstract: An analysis and visualization depicts how an application is leveraging computer processor cores in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime. Information regarding processes or threads running on the processor cores over time is received, analyzed, and presented to indicate portions of processor cores that are used by the application, idle, or used by other processes in the system. The analysis and visualization can help a developer understand contention for processor resources, confirm the degree of concurrency, or identify serial regions of execution that might provide opportunities for exploiting parallelism.

Abstract: The visualization of a storage access on a timeline that represents various disk access events, such as a storage read event, or a storage write event. The storage access timeline may be formulated using event data gathered regarding storage access events, such as storage read requests, or storage write requests. The timeline may be displayed in conjunction with non-storage events, such as thread events, process events, processor events, or such, in order to give a visual indication of what is causing the storage access events. There may even be a control for displaying an identification of the file being accessed for one or more of the storage access events. With a better understanding of correlation between storage access events and application operation, optimization of the application itself may be achieved to more efficiently interface with the storage medium.

Abstract: Analyzing the performance of multi-threaded applications. An analysis and visualization of thread executions is performed on a graphical timeline using samples of thread execution. This allows users to understand when their application threads are executing, what they were executing, the degree of concurrency in thread execution, and the order in which work is performed in their application. The visualizations and analysis also allow users to sample thread execution contexts using a graphical user interface, as well as the generation of execution profile reports that may be filtered for a specific time range of execution and a subset of the threads running in the application.

Abstract: An analysis and visualization is used to depict how a concurrent application executes threads on processor cores over time. With the analysis and visualization, a developer can readily identify thread migrations and thread affinity bugs that can degrade performance of the concurrent application. An example receives information regarding processes or threads running during a selected period of time. The information is processed to determine which processor cores are executing which threads over the selected period of time. The information is analyzed and executing threads for each core are depicted as channel segments over time, and can be presented in a graphical display. The visualization can help a developer identify areas of code that can be modified to avoid thread migration or to reduce thread affinity bugs to improve processor performance of concurrent applications.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: The use of marker(s) in the source code of a program under evaluation. A representation of the marker(s) remains in the binary version of the program under evaluation. During execution, upon executing the marker, data is gathered regarding the timeline of the execution of the marker in the context of overall timeline of execution. A visualization of the marker is then displayed that illustrates the execution of the marker in the context of a larger timeframe of execution. Optionally, the marker may be associated with text, or other data, at least some of which being rendered with the visualization. Accordingly, an application developer, or indeed anyone evaluating the program, may place markers within source code and/or evaluate the timeline of execution of those markers.