Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.

Abstract: IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

Abstract: An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.