Abstract: A server system includes a PCH, a BMC, a BIOS with a write protect end, and a controlling circuit. The BIOS includes a write protect end. The BMC includes a memory portion storing updated server data. The BIOS is electrically connected to the PCH and is electrically connected to the BMC. The controlling circuit includes a first input end and an output end. The first input end is electrically connected to the PCH. The output end is electrically connected to the write protect end. The controlling circuit is configured so that when an error in the BIOS is detected, the write protect end is opened and the BIOS is updated from the memory portion of the BMC.

Abstract: An interface device includes a motherboard, a DVI female interface, a DVI male interface, a display, and an eSATA connector. The motherboard includes a SATA controller having at least one group of differential signal pins. The DVI female interface is electronically coupled to the group of differential signal pins. The DVI male interface is coupled to the DVI female interface. The display is electronically coupled to the DVI male interface. The eSATA connector is positioned on a display and includes at least one group of differential signal pins electrically coupled to the DVI male interface. The differential signal pins of the eSATA connector configured to be in communication with the differential signal pins of the SATA controller via the DVI male interface and the DVI female interface.

Abstract: A server system includes a PCH, a BMC, a BIOS with a write protect end, and a controlling circuit. The BIOS includes a write protect end. The BMC includes a memory portion storing updated server data. The BIOS is electrically connected to the PCH and is electrically connected to the BMC. The controlling circuit includes a first input end and an output end. The first input end is electrically connected to the PCH. The output end is electrically connected to the write protect end. The controlling circuit is configured so that when an error in the BIOS is detected, the write protect end is opened and the BIOS is updated from the memory portion of the BMC.

Abstract: A method for testing Bit Error Rate (BER) of a network module of a communication device includes executing a BER test program to begin a BER test; obtaining a current time and a test data of the BER test program; recording the current time and the test data corresponding to the current time in the test data recording document. The method also determines whether a time interval between the current time and a time when a last test data was recorded is greater than a predetermined value, and if so records a new time and a new test data.

Abstract: A delay circuit for power sequencing in a computer includes an oscillator; an input pin; a counter; a register; and a comparing controller. The counter detects a voltage of the input pin when each clock signal arrives, resets a number counted by the counter when the voltage of the input pin is detected at logic-low electrical level, and adds a predetermined number when the voltage of the input pin is detected at logic-high electrical level. The controller compares the total number counted by the counter with a preset number, and outputs a control signal when the numbers match. The control signal controls a connected logic circuit to work according to a power sequence.