Patents by Inventor He Dong

He Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9002692
    Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Synopsys, Inc.
    Inventors: He Dong, Michael Z. Chui, Shan Yuan
  • Publication number: 20150074385
    Abstract: A server system includes a PCH, a BMC, a BIOS with a write protect end, and a controlling circuit. The BIOS includes a write protect end. The BMC includes a memory portion storing updated server data. The BIOS is electrically connected to the PCH and is electrically connected to the BMC. The controlling circuit includes a first input end and an output end. The first input end is electrically connected to the PCH. The output end is electrically connected to the write protect end. The controlling circuit is configured so that when an error in the BIOS is detected, the write protect end is opened and the BIOS is updated from the memory portion of the BMC.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 12, 2015
    Inventors: SHENG-CUN ZHENG, HE-DONG LV, HONG-LIAN HUANG, JIAN-SHE SHEN
  • Publication number: 20140362895
    Abstract: A method for testing Bit Error Rate (BER) of a network module of a communication device includes executing a BER test program to begin a BER test; obtaining a current time and a test data of the BER test program; recording the current time and the test data corresponding to the current time in the test data recording document. The method also determines whether a time interval between the current time and a time when a last test data was recorded is greater than a predetermined value, and if so records a new time and a new test data.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: SHENG-CUN ZHENG, HE-DONG LV, HONG-LIAN HUANG
  • Patent number: 8868395
    Abstract: In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: October 21, 2014
    Assignee: Synopsys, Inc.
    Inventors: He Dong, Michael Z. Chui, Andrey Y. Tarasevich
  • Publication number: 20140173316
    Abstract: A delay circuit for power sequencing in a computer includes an oscillator; an input pin; a counter; a register; and a comparing controller. The counter detects a voltage of the input pin when each clock signal arrives, resets a number counted by the counter when the voltage of the input pin is detected at logic-low electrical level, and adds a predetermined number when the voltage of the input pin is detected at logic-high electrical level. The controller compares the total number counted by the counter with a preset number, and outputs a control signal when the numbers match. The control signal controls a connected logic circuit to work according to a power sequence.
    Type: Application
    Filed: June 19, 2013
    Publication date: June 19, 2014
    Inventors: SHENG-CUN ZHENG, HE-DONG LV, AN-LIN ZHOU
  • Publication number: 20140147655
    Abstract: Methods are provided for vapor deposition coating of hydrophobic materials and applications thereof. The method for making a hydrophobic material includes providing a natural mineral, providing a silicone-based material, heating the silicone-based material to release vaporous molecules of the silicone-based material, and depositing the vaporous molecules of the silicone-based material to form a layer of the silicone-based material on surfaces of the natural mineral.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 29, 2014
    Applicant: Innovanano, Inc.
    Inventors: Jikang Yuan, He Dong
  • Patent number: 8673393
    Abstract: Methods are provided for vapor deposition coating of hydrophobic materials and applications thereof. The method for making a hydrophobic material includes providing a natural mineral, providing a silicone-based material, heating the silicone-based material to release vaporous molecules of the silicone-based material, and depositing the vaporous molecules of the silicone-based material to form a layer of the silicone-based material on surfaces of the natural mineral.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: March 18, 2014
    Assignee: InnovaNano, Inc.
    Inventors: Jikang Yuan, He Dong
  • Publication number: 20130246015
    Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: Synopsys, Inc.
    Inventors: He Dong, Michael Z. Chui, Shan Yuan
  • Publication number: 20130220764
    Abstract: A food processor or a chopper has a rotating blade, a motor, an intermediate shaft driven by the motor and an output shaft driving the blade. A first clutch member is coupled with the intermediate shaft, and a second clutch member is coupled with the output shaft. The clutch members are movable from an engaged position for driving the output shaft from the motor and a disengaged position for disengaging the output shaft from the motor. A safety interlock mechanism enables and disables the motor. A clutch lever is operable with the safety interlock to move the clutch members between the engaged and disengaged positions such that when the motor is enabled the clutch members are engaged for driving the output shaft from the motor and when the motor is disabled the first and second clutch members are disengaged for disengaging the output shaft from the motor.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Inventors: Mei Chee June Choi, He Dong
  • Publication number: 20130121917
    Abstract: The present invention provides a conjugate having a peptide with from about 10 to about 100 amino acids, wherein the peptide adopts a helical structure. The conjugate also includes a first polymer covalently linked to the peptide, and a hydrophobic moiety covalently linked to the N-terminus of the peptide, wherein the hydrophobic moiety comprises a second polymer or a lipid moiety. The present invention also provides helix bundles form by self-assembling the conjugates, and particles formed by self-assembling the helix bundles. Methods of preparing the helix bundles and particles are also provided.
    Type: Application
    Filed: September 11, 2012
    Publication date: May 16, 2013
    Applicant: Lawrence Berkeley National Laboratory
    Inventors: Ting Xu, He Dong, Jessica Shu
  • Publication number: 20120292256
    Abstract: Methods are provided for vapor deposition coating of hydrophobic materials and applications thereof. The method for making a hydrophobic material includes providing a natural mineral, providing a silicone-based material, heating the silicone-based material to release vaporous molecules of the silicone-based material, and depositing the vaporous molecules of the silicone-based material to form a layer of the silicone-based material on surfaces of the natural mineral.
    Type: Application
    Filed: June 8, 2009
    Publication date: November 22, 2012
    Inventors: Jikang Yuan, He Dong
  • Publication number: 20100106476
    Abstract: In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 29, 2010
    Applicant: Synopsys, Inc.
    Inventors: He Dong, Michael Z. Chui, Andrey Y. Tarasevich