Patents by Inventor He-Yuan Lin

He-Yuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230370643
    Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: obtaining a plurality of MPDUs, wherein the plurality of MPDUs corresponds to at least one I-frame and at least one P-frame; selectively duplicating the MPDUs corresponding to the I-frame to generate a plurality of duplicated MPDUs; and aggregating the plurality of MPDUs and the plurality of duplicated MPDUs in at least one PPDU.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 16, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ying-You Lin, Chiao-Chih Chang, He-Yuan Lin
  • Publication number: 20190378477
    Abstract: An image processing system suitable for accessing a main memory includes a cache, an image processing circuit and a memory controller. The memory controller includes a hit calculating circuit, a deciding circuit and a fetching circuit. In response to a data request issued by the image processing circuit for a set of target image data, the hit calculating circuit calculates a hit rate of the set of target image data in the cache. The deciding circuit generates a prefetch decision according to the hit rate to indicate whether to perform a prefetch procedure. The fetching circuit selectively performs the prefetch procedure on the main memory according to the prefetch decision.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 12, 2019
    Inventor: He-Yuan LIN
  • Patent number: 10225579
    Abstract: A video encoding apparatus for encoding a plurality of image blocks in a video frame includes an intra-frame prediction module, a transformation module and a quantization module. The intra-frame prediction module performs intra-frame prediction on the image blocks to generate a plurality of residual blocks. The transformation module performs a transformation on a target residual block along a predetermined direction according to a transformation matrix to generate a transformation result. The transformation matrix is a product of an initial transformation matrix and a secondary transformation matrix. The initial transformation matrix corresponds to a one-dimensional initial transform performed along the predetermined direction in a two-dimensional initial transform. The secondary transformation matrix corresponds to a one-dimensional secondary transform performed along the predetermined direction in a two-dimensional secondary transform. The quantization module quantizes the transformation result.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 5, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: He-Yuan Lin
  • Patent number: 10116952
    Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 30, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: He-Yuan Lin, Ya-Ting Yang, Yi-Shin Tung
  • Publication number: 20180199031
    Abstract: A video encoding apparatus is provided. A controller in the video encoding apparatus includes a sum calculating circuit, a data amount estimating circuit, and an evaluating circuit. Each of a plurality of intra-prediction and motion compensation modes corresponds to a set of transformed/quantized residual data. The sum calculating circuit calculates, for each set of transformed/quantized residual data, a sum of absolute values of non-zero elements therein and a sum of coordinate values of these non-zero elements relative to a reference point. The data amount estimating circuit generates, for each intra-prediction and motion compensation mode, an estimated data amount according to the sum of absolute values and the sum of absolute values of the coordinate values of corresponding transformed and quantized residual data. The evaluating circuit selects a best mode from the plurality of intra-prediction and motion compensation modes according to the plurality of estimated data amounts.
    Type: Application
    Filed: October 26, 2017
    Publication date: July 12, 2018
    Inventor: He-Yuan LIN
  • Publication number: 20180199002
    Abstract: A video processing apparatus includes a down-sampling circuit, a combining circuit, a metadata generating circuit, and an encoder. The down-sampling circuit down-samples P videos according to predetermined picture layout information of K picture layouts. Each of the videos corresponds to a television program. The combining circuit combines the P down-sampled videos according to the predetermined picture layout information to generate combined videos corresponding to the K picture layouts. The metadata generating circuit generates metadata that describes television program information corresponding to the picture layouts according to the predetermined picture layout information. The encoder encodes the combined videos and the metadata to image data that conforms to a predetermined broadcast format for a television broadcasting system to broadcast.
    Type: Application
    Filed: September 25, 2017
    Publication date: July 12, 2018
    Inventors: Yi-Shin Tung, Tzu-Jung Huang, He-Yuan Lin
  • Patent number: 10015493
    Abstract: An encoding apparatus includes an intra-prediction module, a transform module and a control module. The intra-prediction module performs intra-prediction on an image block in a video frame according to a plurality of sets of reference image data to generate a residual block. The reference image data includes a set of reference image data corresponding to a predetermined side of the image block. The transform module performs preliminary transform on the residual block to generate a preliminary transform coefficient matrix. According to whether at least one of the reference image data corresponding to the predetermined side is generated according to image data of an adjacent pixel of the image block, the control module determines whether secondary transform perpendicular to the predetermined side is to be performed on a low-frequency component sub-matrix in the preliminary transform coefficient matrix.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 3, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Publication number: 20180184090
    Abstract: A binary arithmetic coding apparatus is implemented in a video encoder chip. The binary arithmetic coding apparatus outputs a code word according to a syntax element value, and includes a look-up table (LUT), a suffix generator and a combiner. The LUT outputs a first binary string according to the syntax element value. The suffix generator performs exp-Golomb binarization on the syntax element value to generate a second binary string. When the syntax element value is smaller than or equal to a threshold, the first binary string is outputted as the code word. When the syntax element value is greater than the threshold, the combiner combines the first binary string and the second binary string to form the code word.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 28, 2018
    Inventors: Pai-Chin LIU, He-Yuan LIN
  • Publication number: 20180054626
    Abstract: A method for decoding audio/video data in an Audio Video coding Standard (AVS) system is provided. A predetermined upper limit of an offset shift, greater than zero and smaller than an upper limit of a range shift, is provided. Whether to terminate an offset pre-fetching process is determined according to whether an offset shift reaches the upper limit of the offset shift. After offset shift pre-fetching process is terminated, a most significant bit (MSB) of a valid offset is preserved. The preserved valid MSB of the valid offset is used as a reference when a symbol to be decoded is determined to be a most probable symbol or a least probable symbol.
    Type: Application
    Filed: March 15, 2017
    Publication date: February 22, 2018
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Publication number: 20180052773
    Abstract: A memory managing method for a cache including multiple storage regions is provided. Each of the storage regions includes multiple cache lines, and corresponds to multiple image blocks included in an original image frame. In response to a request for storing compressed data of an image block into the cache, a target storage region corresponding to the image block is selected from the multiple storage regions. A target applied sequence of the cache lines for the image block is determined. The compressed data of the image block is stored into the target storage region in a way that the compressed data of the image block is stored in the target storage region as conformed to the target applied sequence of the cache lines.
    Type: Application
    Filed: February 9, 2017
    Publication date: February 22, 2018
    Inventor: He-Yuan Lin
  • Patent number: 9794580
    Abstract: A signal processing system for motion pictures includes a signal processing module, a cache, an analysis module and a control module. The signal processing module performs a signal processing process on motion picture data. The cache temporarily stores a set of reference data that is required for processing the motion picture during the signal processing process. The analysis module generates cache miss analysis information associated with the signal processing process and the cache. The control module determines an index content configuration of the cache according to the cache miss analysis information.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: October 17, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventor: He-Yuan Lin
  • Publication number: 20170295368
    Abstract: A bit rate controlling method applied to a video encoding device includes: establishing a parameter table according to a first frame-level parameter corresponding to a first frame, and storing the parameter table to a look-up table (LUT) unit of the video encoding device; reading the parameter table stored in the LUT unit to obtain at least one encoding parameter corresponding to an encoding block in the first frame according to the parameter table and a target parameter of the encoding block; and encoding the encoding block of the first frame according to the at least one encoding parameter.
    Type: Application
    Filed: May 31, 2016
    Publication date: October 12, 2017
    Inventors: Shu-Wei Teng, Chia Chiang Ho, He-Yuan Lin
  • Publication number: 20170201707
    Abstract: A television managing apparatus cooperating with a remote controller includes a receiver and a controller. The receiver receives an instruction sent from the remote controller. The controller actives a performance optimization process in response to each latest instruction that the receiver receives.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 13, 2017
    Inventors: Yi-Shin Tung, He-Yuan Lin, Hung-Wei Yang
  • Publication number: 20170155918
    Abstract: A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.
    Type: Application
    Filed: January 11, 2016
    Publication date: June 1, 2017
    Inventors: He-Yuan LIN, Ya-Ting YANG, Yi-Shin TUNG
  • Patent number: 9525890
    Abstract: A decoding method for an audio video coding standard (AVS) system is provided. According to a stop-fetching criterion, a stop-fetching flag is set to an enabled status or a disabled status. In an offset fetching procedure, it is determined whether an offset value is smaller than a threshold and whether the stop-fetching is in the disabled status. When a determination result is affirmative, one subsequent bit is fetched for the offset value, an offset shift value is correspondingly increased, and the determination step is iterated. When the determination result is negative, the offset fetching procedure is terminated. Next, it is determined whether a decoding result is a least probable symbol (LPS) or a most probable symbol (MPS).
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 20, 2016
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Patent number: 9483415
    Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 1, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yi-Shin Tung, He-Yuan Lin, Jia-Wei Lin, Hung-Wei Yang
  • Publication number: 20160088310
    Abstract: A video encoding apparatus for encoding a plurality of image blocks in a video frame includes an intra-frame prediction module, a transformation module and a quantization module. The intra-frame prediction module performs intra-frame prediction on the image blocks to generate a plurality of residual blocks. The transformation module performs a transformation on a target residual block along a predetermined direction according to a transformation matrix to generate a transformation result. The transformation matrix is a product of an initial transformation matrix and a secondary transformation matrix. The initial transformation matrix corresponds to a one-dimensional initial transform performed along the predetermined direction in a two-dimensional initial transform. The secondary transformation matrix corresponds to a one-dimensional secondary transform performed along the predetermined direction in a two-dimensional secondary transform. The quantization module quantizes the transformation result.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 24, 2016
    Inventor: He-Yuan Lin
  • Publication number: 20160014414
    Abstract: An encoding apparatus includes an intra-prediction module, a transform module and a control module. The intra-prediction module performs intra-prediction on an image block in a video frame according to a plurality of sets of reference image data to generate a residual block. The reference image data includes a set of reference image data corresponding to a predetermined side of the image block. The transform module performs preliminary transform on the residual block to generate a preliminary transform coefficient matrix. According to whether at least one of the reference image data corresponding to the predetermined side is generated according to image data of an adjacent pixel of the image block, the control module determines whether secondary transform perpendicular to the predetermined side is to be performed on a low-frequency component sub-matrix in the preliminary transform coefficient matrix.
    Type: Application
    Filed: June 5, 2015
    Publication date: January 14, 2016
    Inventors: He-Yuan Lin, Yi-Shin Tung
  • Patent number: 9092384
    Abstract: The quantifying method for intrinsic data transfer rate of algorithms is provided. The provided quantifying method for an intrinsic data transfer rate includes steps of: detecting whether or not a datum is used; providing a dataflow graph G including n vertices and m edges, and a Laplacian matrix L having ixj elements L(i,j) when the datum is not reused, wherein each of the vertices represents one of an operation and a datum, each of the edges represents a data transfer, and vi is the ith vertex; and using the Laplacian matrix L to estimate a maximum quantity of the intrinsic data transfer rate.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 28, 2015
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun Lee, He-Yuan Lin
  • Publication number: 20150139326
    Abstract: A signal processing system for motion pictures includes a signal processing module, a cache, an analysis module and a control module. The signal processing module performs a signal processing process on motion picture data. The cache temporarily stores a set of reference data that is required for processing the motion picture during the signal processing process. The analysis module generates cache miss analysis information associated with the signal processing process and the cache. The control module determines an index content configuration of the cache according to the cache miss analysis information.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventor: He-Yuan Lin