Abstract: A device includes a virtual power line directly connected to each bitcell in a group of bitcells and a group of transistor switches connected between the virtual power line and a power supply. The device also includes a delay circuit, a first wakeup detector, and a plurality of main input-output (MIO) controllers. The delay circuit is coupled to the gate terminal of each transistor switch of the group of transistor switches. The first wakeup detector is configured to generate a first trigger signal in response to receiving a signal from the delay circuit. The plurality of main input-output (MIO) controllers is configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches. A gate terminal of each wakeup switch in the first group of wakeup switches is configured to receive the first trigger signal.

Abstract: Disclosed herein is a method for determining whether a subject is suffering from, or is at risk of developing breast cancer, wherein the method comprises detecting differential expression levels of at least two or more miRNA markers from a biological sample. Also disclosed herein is a method of determining whether a subject is suffering from, or is at risk of developing, breast cancer based on miRNA expression.

Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.

Abstract: Various embodiments are directed to frequency and voltage tuning for systems with multiple application-specific integrated circuits (ASICs) and disclosed herein may be applied to multi-AIC systems in a variety of applications, such as high-performance computing, artificial intelligence, graphics applications, and cryptocurrency or blockchain mining functions.

Abstract: A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

Abstract: Disclosed is a method for nanomorphological modification of polyether ether ketone (PEEK) surface by hot pressing, relating to the technical field of biomaterials. The method includes the following steps: S1, preparing SiO2 nanospheres; S2, uniformly laying the SiO2 nanospheres prepared in the S1 on a surface of a PEEK material; S3, heating the surface of the PEEK material to a temperature higher than a glass phase transition temperature, then carrying out hot pressing to embed the SiO2 nanospheres into the surface of the PEEK material, and naturally cooling at room temperature after the hot pressing; S4, after cooling, using NaOH solution to corrode and remove the SiO2 nanospheres on the surface of the PEEK material after hot pressing in S3 to form a structure with nanoconcaves, then obtaining a hot-pressed modified PEEK material.

Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.

Abstract: This disclosure provides an energy storage apparatus, an energy storage apparatus control method, and a photovoltaic system. The energy storage apparatus includes: a plurality of battery clusters, a plurality of conversion units, a start unit, and a controller. The controller includes a plurality of control units. The start unit is configured to: after receiving a start signal, control a control switch in at least one battery cluster to close, to start a control unit corresponding to the battery cluster. The control unit is configured to: determine, based on a state of the control switch in the battery cluster, whether a black start mode is on; and when determining that the black start mode is on, control a DC-DC converter in the corresponding conversion unit to release electric energy stored in a battery pack in the corresponding battery cluster, to energize a direct current bus.

Abstract: An instrumented trail-making task (iTMT) platform includes a wearable sensor and interactive interface technology configured to identify cognitive-cognitive impairment in individuals such as older adults. The iTMT platform may be programmed with neuropsychological tests for assessing individuals. The iTMT may provide information on visual search, scanning, speed of processing, mental flexibility, and/or executive functions as well as physical biomarkers of motor performance including slowness, weakness, exclusion, and/or motor planning error. Results of tests administered by the iTMT system may be reported to a patient or caregiver and used in identifying cogni-tive-motor impairment among individuals suffering from cognitive impairment, dementia, and/or those with frailty status, and/or cognitive frailty, and/or high risk of falling, and/or high likelihood of decline in cognitive-motor over time.

Abstract: A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.

Abstract: An energy storage system includes one or more energy storage unit clusters, and the energy storage unit cluster includes at least two energy storage modules connected in series. The energy storage system further includes a first bus, a second bus, and a centralized monitoring system of the energy storage unit cluster, where the second bus is a direct current bus. The energy storage unit cluster is coupled to the first bus by using a first converter. One energy storage module includes one energy storage element group and one DC/DC converter, and the energy storage element group is coupled to the second bus by using the DC/DC converter. The centralized monitoring system is connected to the energy storage unit cluster through a control bus, and is configured to control a DC/DC converter in any energy storage module in the energy storage unit cluster.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: This disclosure provides an energy storage apparatus, an energy storage apparatus control method, and a photovoltaic system. The energy storage apparatus includes: a plurality of battery clusters, a plurality of conversion units, a start unit, and a controller. The controller includes a plurality of control units. The start unit is configured to: after receiving a start signal, control a control switch in at least one battery cluster to close, to start a control unit corresponding to the battery cluster. The control unit is configured to: determine, based on a state of the control switch in the battery cluster, whether a black start mode is on; and when determining that the black start mode is on, control a DC-DC converter in the corresponding conversion unit to release electric energy stored in a battery pack in the corresponding battery cluster, to energize a direct current bus.

Abstract: A battery system comprises a first busbar, at least one battery rack, and a control circuit are included. The battery rack includes a plurality of battery units. Each battery unit includes a battery module, a connection switch K1, and an isolation switch K2. The connection switch K1 is connected in series to the battery module to form a first branch, and the isolation switch K2 is connected in parallel to the first branch. The control circuit is connected to control ends of the connection switch K1 and the isolation switch K2, and is configured to: control, based on a first voltage required by the load, connection switches K1 and isolation switches K2 of N battery units in the battery rack, to make an output voltage of the first busbar meet the first voltage required by the load.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

Abstract: A method for controlling an energy storage system includes: determining that a first battery cluster in a plurality of battery clusters needs to be calibrated; and controlling, based on a state of charge SOC of the first battery cluster and a current charging or discharging state of the energy storage system, the first battery cluster to be charged or discharged or to be in a standby state, so that the first battery cluster satisfies a SOC calibration condition. In the method, charging, discharging, or standby-state control needs to be performed on only one battery cluster that needs to be calibrated in the energy storage system, independent decoupling management is implemented on the battery cluster, and normal running of the energy storage system is not affected. This enables the battery cluster to quickly satisfy the SOC calibration condition and can improve SOC accuracy of the energy storage system.

Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.