Patents by Inventor He Zhou

He Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250104765
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250104766
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250098139
    Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Yan-Bo SONG
  • Publication number: 20250092627
    Abstract: The present invention relates to pile foundations and provides an intelligent construction control method and system for jet grouting piles based on stratum information inversion. This method integrates multi-source sensing components and local transmission to perceive real-time drilling information to a data integration terminal. Using engineering soil layer data as training samples, a machine learning algorithm correlates perception information with geological conditions, judging and outputting stratum conditions in real time. An XGBoost model quickly and accurately identifies soil layers at the site. Based on big data matching of a cloud platform, an optimal construction parameter database is established, and the optimal combination of parameters is acquired through algorithm matching.
    Type: Application
    Filed: July 4, 2024
    Publication date: March 20, 2025
    Applicants: SHANDONG UNIVERSITY, SHANDONG JIANZHU UNIVERSITY
    Inventors: Peizhi ZHUANG, Kangxu WANG, He YANG, Jingjing YIN, Xiuguang SONG, Chaoji LI, Chong ZHOU, Yuanshun QIAN, Chao LI, Mingpeng LIU
  • Patent number: 12255721
    Abstract: A method which may be performed by a base station, may include obtaining a predicted transmission configuration indicator (TCI) subset for a user equipment (UE); and determining the TCI subset corresponding to the UE based on the predicted TCI subset. The step of obtaining the predicted TCI subset in the solution may be implemented by using a trained artificial intelligence model. Since the beams in the predicted TCI subset may fit the movement trend of the UE, then the target serving beam for the UE when performing serving beam switching may belong to the predicted TCI subset with a greater possibility, thus reducing the occurrence of high delay scenarios when the UE performs the serving beam switching, and thus reducing the beam switching delay.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: March 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Liying Zhou, Lei Wang, Yiyan Zhang, He Wang, Songhui Shen, Chaeman Lim
  • Publication number: 20250078885
    Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou WAN, Xiu-Li YANG, Pei-Le LI, Ching-Wei WU
  • Publication number: 20250078905
    Abstract: A memory device, comprising: a first driving circuit configured to provide a first current signal to a first node according to a decoder signal; a second driving circuit configured to provide a second current signal to a second node according to the decoder signal; and a modulating circuit coupled to the first node and the second node, configured to transmit each of the first current signal and the second current signal to a reference voltage terminal. A method is also disclosed herein. A method is also disclosed herein.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: He-Zhou WAN, Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG
  • Publication number: 20250043307
    Abstract: An expression cassette containing overlapping open reading frames and an application thereof are provided. The overlapping open reading frames are overlapping open reading frames of a first ORF and a second ORF and include in sequence from a 5? end to a 3? end: a first promoter at least used to drive gene transcription of the first ORF; a 5? part of a gene of the first ORF; an intron; and a 3? part of a gene of the second ORF, the intron including a second promoter used only to drive gene transcription of the second ORF. By arranging two promoters in a single expression cassette in the disclosure, the two promoters are used to drive the expression of proteins of the overlapping reading frames and regulate the relative expression time and expression intensity of different proteins.
    Type: Application
    Filed: February 6, 2024
    Publication date: February 6, 2025
    Applicant: GENEVOYAGER (WUHAN) CO., LTD.
    Inventors: He XIAO, Xiaobin HE, Gang HUANG, Xing PAN, Yicheng ZHOU, Liang DU, Mengdie WANG, Huanhuan ZUO, Hao SUN
  • Patent number: 12211586
    Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 28, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
  • Patent number: 12202109
    Abstract: A method of detecting a workpiece jam condition in a pneumatic tool includes striking a workpiece by a blade of the tool, detecting whether a piston to which the blade is attached reaches a predetermined position within a predetermined time, and determining a workpiece jam condition has occurred if the piston does not reach the predetermined position within the predetermined time.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 21, 2025
    Assignee: Techtronic Cordless GP
    Inventors: Ying Xiang Tan, Hai Ling Lin, Xi He, Jin Lin Zhou
  • Patent number: 12198754
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: January 14, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, Lu-Ping Kong, Kuan Cheng, He-Zhou Wan
  • Patent number: 12190940
    Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
  • Patent number: 12190984
    Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Xiu-Li Yang, Ching-Wei Wu, He-Zhou Wan, Ming-En Bu
  • Patent number: 12193206
    Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Yan-Bo Song
  • Patent number: 12183428
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
  • Patent number: 12183432
    Abstract: A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: XiuLi Yang, Ching-Wei Wu, He-Zhou Wan, Kuan Cheng, Luping Kong
  • Patent number: 12184285
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: XiuLi Yang, Kuan Cheng, He-Zhou Wan, Ching-Wei Wu, Wenchao Hao
  • Patent number: 12176062
    Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: December 24, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou Wan, Xiu-Li Yang, Pei-Le Li, Ching-Wei Wu
  • Publication number: 20240371413
    Abstract: A device includes a virtual power line directly connected to each bitcell in a group of bitcells and a group of transistor switches connected between the virtual power line and a power supply. The device also includes a delay circuit, a first wakeup detector, and a plurality of main input-output (MIO) controllers. The delay circuit is coupled to the gate terminal of each transistor switch of the group of transistor switches. The first wakeup detector is configured to generate a first trigger signal in response to receiving a signal from the delay circuit. The plurality of main input-output (MIO) controllers is configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches. A gate terminal of each wakeup switch in the first group of wakeup switches is configured to receive the first trigger signal.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: He-Zhou WAN, XiuLi YANG, Ming-En BU, Mengxiang XU, Zong-Liang CAO
  • Patent number: 12080372
    Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: September 3, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: He-Zhou Wan, Xiuli Yang, Ming-En Bu, Mengxiang Xu, Zong-Liang Cao