Patents by Inventor Heath Stewart
Heath Stewart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11394315Abstract: A Power over Data Lines (PoDL) system provides a DC voltage and differential data signals on the same wire pair. A Powered Device (PD) load is coupled to the wire pair, via a gyrator, for being powered by the DC voltage. The gyrator emulates the DC-coupling properties of inductors using active components. The gyrator includes transistors that are controlled to act as a full-bridge rectifier for ensuring a correct polarity DC voltage is applied to the PD load. Since the transistors operate in saturation and are coupled to be insensitive to differential data signals on the wire pair, the current supplied to the PD load is substantially unaffected by the differential data signals. Negative feedback circuits in the gyrator reduce fluctuations in current through the gyrator due to differential data signals on the wire pair. No inductors are required in the gyrator. A PHY is AC-coupled to the wire pair via capacitors.Type: GrantFiled: August 5, 2020Date of Patent: July 19, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Andrew J. Gardner, Heath Stewart, Gitesh Bhagwat
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Patent number: 11038490Abstract: A PoDL system uses a gyrator for DC coupling of DC power from a PSE to a wire pair, and/or decoupling DC power from a wire pair for a PD. The gyrators obviate the use of discrete inductors for DC-coupling/decoupling and can be formed as an integrated circuit. The gyrators use a small integrated capacitor and invert and multiply the capacitor effect to emulate an inductor. The gyrators present a high impedance to AC current and a low impedance to DC current. Various gyrator designs, such as positive and negative polarity gyrators, and configurations are disclosed. Gyrators are described with analog current limit and power switch control, so multiple functions are integrated on the same IC chip.Type: GrantFiled: March 17, 2020Date of Patent: June 15, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Andrew J. Gardner, Heath Stewart, Gitesh Bhagwat
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Publication number: 20210104953Abstract: A Power over Data Lines (PoDL) system provides a DC voltage and differential data signals on the same wire pair. A Powered Device (PD) load is coupled to the wire pair, via a gyrator, for being powered by the DC voltage. The gyrator emulates the DC-coupling properties of inductors using active components. The gyrator includes transistors that are controlled to act as a full-bridge rectifier for ensuring a correct polarity DC voltage is applied to the PD load. Since the transistors operate in saturation and are coupled to be insensitive to differential data signals on the wire pair, the current supplied to the PD load is substantially unaffected by the differential data signals. Negative feedback circuits in the gyrator reduce fluctuations in current through the gyrator due to differential data signals on the wire pair. No inductors are required in the gyrator. A PHY is AC-coupled to the wire pair via capacitors.Type: ApplicationFiled: August 5, 2020Publication date: April 8, 2021Inventors: Andrew J. Gardner, Heath Stewart, Gitesh Bhagwat
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Patent number: 10868680Abstract: A PoE system includes a PSE connected via a shielded twisted wire pair to a PD, where differential data is transmitted over only the wire pair, and where DC power is transmitted via the wires in the wire pair conducting a DC voltage in parallel while using the shield conductor as ground. A low power handshaking routine is performed by a PSE controller and a PD controller by conducting a source current through the wires in parallel and a return current through the shield conductor. Center tap auto-transformers are used to connect the two wires to the PSE and PD controllers and to a DC voltage source in the PSE. After a successful handshaking routine, the PSE couples the DC voltage source between the wire pair and the shield conductor by closing a first power switch. The PD controller then closes a second power switch to power a load.Type: GrantFiled: August 21, 2018Date of Patent: December 15, 2020Assignee: Analog Devices International Unlimited CompanyInventors: Andrew J. Gardner, Heath Stewart
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Publication number: 20200304106Abstract: A PoDL system uses a gyrator for DC coupling of DC power from a PSE to a wire pair, and/or decoupling DC power from a wire pair for a PD. The gyrators obviate the use of discrete inductors for DC-coupling/decoupling and can be formed as an integrated circuit. The gyrators use a small integrated capacitor and invert and multiply the capacitor effect to emulate an inductor. The gyrators present a high impedance to AC current and a low impedance to DC current. Various gyrator designs, such as positive and negative polarity gyrators, and configurations are disclosed. Gyrators are described with analog current limit and power switch control, so multiple functions are integrated on the same IC chip.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Inventors: Andrew J. Gardner, Heath Stewart, Gitesh Bhagwat
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Patent number: 10547206Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.Type: GrantFiled: October 3, 2017Date of Patent: January 28, 2020Assignee: Linear Technology CorporationInventors: Heath Stewart, Andrew J. Gardner, David Stover, David Dwelley, Jeffrey L. Heath
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Publication number: 20190068385Abstract: A PoE system includes a PSE connected via a shielded twisted wire pair to a PD, where differential data is transmitted over only the wire pair, and where DC power is transmitted via the wires in the wire pair conducting a DC voltage in parallel while using the shield conductor as ground. A low power handshaking routine is performed by a PSE controller and a PD controller by conducting a source current through the wires in parallel and a return current through the shield conductor. Center tap auto-transformers are used to connect the two wires to the PSE and PD controllers and to a DC voltage source in the PSE. After a successful handshaking routine, the PSE couples the DC voltage source between the wire pair and the shield conductor by closing a first power switch. The PD controller then closes a second power switch to power a load.Type: ApplicationFiled: August 21, 2018Publication date: February 28, 2019Inventors: Andrew J. Gardner, Heath Stewart
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Patent number: 9984027Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.Type: GrantFiled: January 29, 2016Date of Patent: May 29, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Publication number: 20180115191Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.Type: ApplicationFiled: October 3, 2017Publication date: April 26, 2018Inventors: Heath Stewart, Andrew J. Gardner, David Stover, David Dwelley, Jeffrey L. Heath
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Patent number: 9860072Abstract: A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.Type: GrantFiled: April 20, 2016Date of Patent: January 2, 2018Assignee: Linear Technology CorporationInventors: Andrew J. Gardner, David M. Dwelley, Heath Stewart
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Patent number: 9667429Abstract: A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.Type: GrantFiled: May 6, 2015Date of Patent: May 30, 2017Assignee: Linear Technology CorporationInventors: David Dwelley, Jeffrey Heath, Heath Stewart, Michael Paul
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Patent number: 9634844Abstract: In a method performed by a PoE system, a PSE is able to detect whether a PD is compatible for receiving power via four wire pairs in the standard Ethernet cable. The PSE provides a current limited voltage to a first and second pair of wires in the cable, during a detection phase, to detect a characteristic impedance of the PD. In the PSE, a first resistor is connected to a third wire pair and a second resistor is connected to a fourth wire pair. During the detection phase, the PSE detects the relative currents through the resistors. If the currents are the same, then the PSE knows the PD is able to receive power via the four wire pairs. The PSE then applies the full PoE voltage to the first and second wire pairs and connects the third and fourth wire pairs to a low voltage via a MOSFET.Type: GrantFiled: January 28, 2015Date of Patent: April 25, 2017Assignee: Linear Technology CorporationInventors: Michael Paul, Jeffrey Heath, David Dwelley, Heath Stewart
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Publication number: 20160337138Abstract: A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.Type: ApplicationFiled: April 20, 2016Publication date: November 17, 2016Inventors: Andrew J. Gardner, David M. Dwelley, Heath Stewart
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Publication number: 20160147693Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.Type: ApplicationFiled: January 29, 2016Publication date: May 26, 2016Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Publication number: 20150326403Abstract: A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.Type: ApplicationFiled: May 6, 2015Publication date: November 12, 2015Inventors: David Dwelley, Jeffrey Heath, Heath Stewart, Michael Paul
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Publication number: 20150215131Abstract: In a method performed by a PoE system, a PSE is able to detect whether a PD is compatible for receiving power via four wire pairs in the standard Ethernet cable. The PSE provides a current limited voltage to a first and second pair of wires in the cable, during a detection phase, to detect a characteristic impedance of the PD. In the PSE, a first resistor is connected to a third wire pair and a second resistor is connected to a fourth wire pair. During the detection phase, the PSE detects the relative currents through the resistors. If the currents are the same, then the PSE knows the PD is able to receive power via the four wire pairs. The PSE then applies the full PoE voltage to the first and second wire pairs and connects the third and fourth wire pairs to a low voltage via a MOSFET.Type: ApplicationFiled: January 28, 2015Publication date: July 30, 2015Inventors: Michael Paul, Jeffrey Heath, David Dwelley, Heath Stewart
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Patent number: 7945722Abstract: Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.Type: GrantFiled: September 29, 2010Date of Patent: May 17, 2011Assignee: Internet Machines, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Publication number: 20110016258Abstract: Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.Type: ApplicationFiled: September 29, 2010Publication date: January 20, 2011Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7814259Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.Type: GrantFiled: August 20, 2008Date of Patent: October 12, 2010Assignee: Internet Machines, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7590791Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.Type: GrantFiled: August 21, 2008Date of Patent: September 15, 2009Assignee: Topside Research, LLCInventors: Heath Stewart, Chris Haywood, Michael De La Garrigue, Nadim Shaikli, Ken Wong, Bao Vuong, Thomas Reiner, Adam Rappoport