Abstract: A counter is used to concurrently refresh a video display and a memory associated with such video display. Address bits are output from the counter to the sync decode logic used to refresh the display as well as to multiplexing means connected to the associated memory. The multiplexing means has three pairs of inputs. The first pair of inputs comprises refresh addresses from the counter for refreshing the memory array. The second pair of inputs to the multiplexing means comprises memory update addresses for writing new information into the memory. A third pair of inputs to the multiplexing means performs two functions. The first function enables the multiplexing means to output either the update addresses or the refresh addresses depending on the state of such inputs. The second function of the third pair of inputs is to identify the output of said multiplexing means as either a row address or a column address to the associated memory.