Patents by Inventor Hector X. Roman

Hector X. Roman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for compensation and current spreading correction in shared drain multi-channel load switch
    Patent number: 10366987
    Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 30, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: David J. Baldwin, Hector X. Roman, Md. Abidur Rahman
  • Methods and Apparatus for Compensation and Current Spreading Correction in Shared Drain Multi-Channel Load Switch
    Publication number: 20170030948
    Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.
    Type: Application
    Filed: July 15, 2016
    Publication date: February 2, 2017
    Inventors: David J. Baldwin, Hector X. Roman, Md. Abidur Rahman