Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value.

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value.

Abstract: A data processing apparatus and method for handling interrupts is provided, the apparatus having an interrupt controller operable to receive interrupts generated by a number of interrupt sources, and to determine based on predetermined criteria whether to output an interrupt request signal. A processing unit is provided which is operable upon receipt of the interrupt request signal to perform an interrupt service routine for a selected one of the received interrupts in order to generate an interrupt response for the corresponding interrupt source. Timer logic is also provided which is operable upon receipt of an interrupt generated by an associated interrupt source to produce a timing indication.

Abstract: A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

Abstract: A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse.

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.

Abstract: Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or instruction access to at least one predetermined address and in response to not detecting said data or instruction access within said predetermined time, said control logic is operable to send a control signal to said data processor, said control signal controlling said data processor to perform a predetermined operation.

Abstract: The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream.

Abstract: A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.

Abstract: A data processor comprises a register bank containing a plurality of “n” bit registers for storing data items, a set of registers within the register bank being allocatable to hold stack data items from a portion of the stack, and each register in the set storing as an n-bit value stack data items of the first or second type. An arithmetic logic unit executes operations upon data items held in the registers and a decoder decodes a stack-based instruction to specify a number of operations to be executed by the arithmetic logic unit upon one or more stack data items held in predetermined registers in the set. Further, a stack controller is arranged to control movement of stack data items between the stack and the set of registers, and is responsive to the decoder causing one or more stack data items to be held in the predetermined registers.

Abstract: A technique for decoding an encoded data stream representing an original sequence of data bits, each data bit comprising a plurality of codes, each code being dependent on a current data bit and a first predetermined number of preceding data bits in the original sequence. Scores are provided indicating the likelihood that a corresponding state represents the first predetermined number of preceding data bits. The scores are arranged in an initial ordering. A first plurality of score bit slices are stored to collectively represent the initially ordered scores, each score bit slice containing a predetermined bit from each of the scores. The scores are then reordered and a second plurality of score bit slices are stored to collectively represent the reordered scores. By this approach, all the scores are updated simultaneously.

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.

Abstract: The present invention provides a data processing apparatus and method for executing stack-based instructions specifying operations to be executed upon stack data items held in a stack, a first type of stack data item having a first size and a second type of stack data item having a second size. The data processing apparatus comprises a register bank containing a plurality of “n” bit registers for storing data items, a set of registers within the register bank being allocatable to hold stack data items from a portion of the stack, and each register in the set being able to store as an n-bit value a stack data item of the first type or a stack data item of the second type. An arithmetic logic unit is then provided for executing operations upon data items held in the registers.

Abstract: A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a branch search strategy to successively narrow the possibilities for the highest priority bit at each search level until a single bit within the status word is identified corresponding to the highest priority interrupt signal. The programmable masks may be programmed for a particular configuration of the priorities of the respective bits within the status word. The branch search strategy provides a reduced maximum interrupt latency and improved predictability in the interrupt latency.

Abstract: A technique for decoding an encoded data stream representing an original sequence of data bits is provided, wherein the encoded data stream comprises a plurality of codes, each code being dependent on a current data bit and a first predetermined number of preceding data bits in the original sequence. For each of a number of possible states of the first predetermined number of preceding data bits, a score is provided indicating the likelihood that the corresponding state represents the first predetermined number of preceding data bits. The scores are arranged in an initial ordering. Upon receipt of a code given each of the two possible values of the current data bit in the received code, two update values are determined for each state indicating the likelihood, based on the received code, that that state represents the first predetermined number of bits.