Patents by Inventor Hee Bong Lee
Hee Bong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950383Abstract: A display apparatus according to a concept of the disclosure includes: a display panel configured to display an image in a front direction; a top chassis positioned in a front direction of the display panel; a bottom chassis positioned in a rear direction of the display panel; a rear cover covering a rear side of the bottom chassis; and a stand member being accommodatable in the rear cover and selectively coupled with a rear surface of the rear cover, wherein the rear cover includes an accommodating portion in which the stand member is accommodated and a coupling portion coupled with the stand member, and the stand member includes an inserting protrusion which is inserted into the accommodating portion and the coupling portion.Type: GrantFiled: August 27, 2019Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Bong Kim, Dong Wook Kim, Ji-Gwang Kim, Tae-Hun Kim, Yong Gu Do, Jeong Woo Park, Gil Jae Lee, Sang Young Lee, Pil Kwon Jung, Su-An Choi
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Publication number: 20240085007Abstract: Proposed is a detachable lighting device including lighting units. The positions of the lighting units are changeable along a mounting rail within an interior space. The number of the lighting units and the mounting positions of the lighting units are adjustable. Accordingly, occupants within the interior space adjust light distribution as desired by each occupant.Type: ApplicationFiled: November 11, 2022Publication date: March 14, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, LS Automotive Technologies Co., Ltd.Inventors: Sung Ho Park, Ki Bong Lee, Su Gyeong Im, Hee Youl An, Kyeong Sik Kim
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Patent number: 8848596Abstract: Embodiments for providing a method of controlling timing of a downlink backhaul sub-frame and a relay system for the same are disclosed. According to the present invention, a control signal is transmitted to user equipment during a control symbol period of a sub-frame and a data starting point of the sub-frame is set after a time (SG1) for switching from a transmission mode to a reception mode to receive backhaul data of a base station during a backhaul symbol period. Timing of a transmission sub-frame and a reception sub-frame is delayed by the SG1. A sum of a length of the SG1 and a time (SG2) for switching from the reception mode to the transmission mode is shorter than a length of a symbol having a normal CP. At this time, the lengths of the SG1 and the SG2 are identical to each other or the length of the SG2 is shorter than the length of the SG1. In such a case, the backhaul data are received up to a last symbol period of backhaul symbols of the reception sub-frame.Type: GrantFiled: January 28, 2011Date of Patent: September 30, 2014Assignee: LG-Ericsson Co., Ltd.Inventors: Hong Sup Shin, Young Jun Kim, Sang Ha Kim, Il Doo Chang, Hee Bong Lee
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Patent number: 8741927Abstract: The present invention relates to a novel method for preparing a compound of formula (2) as the intermediate, which can be effectively used for preparation of a compound of formula (1) exhibiting good inhibitory activity against dipeptidyl peptidase IV enzyme.Type: GrantFiled: August 25, 2011Date of Patent: June 3, 2014Assignee: LG Life Sciences Ltd.Inventors: Bong Chan Kim, Kyu Young Kim, Hee Bong Lee, Ji Eun An, Kyu Woong Lee
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Patent number: 8548514Abstract: The present invention relates to a method for reducing a resource element group (REG) size, which is used at a control channel element (CCE) for a relay physical downlink control channel (R-PDCCH), for the purpose of easy interleaving by a physical resource block (PRB) unit for the R-PDCCH, and a mobile telecommunication system for the same. The mobile telecommunication system of the present invention includes reducing the CCE size to 8 REGs or less of the R-PDCCH to be included in a single PRB.Type: GrantFiled: January 28, 2011Date of Patent: October 1, 2013Assignee: LG-Ericsson Co., Ltd.Inventors: Sang Ha Kim, Hong Sup Shin, Young Jun Kim, Byoung-Seong Park, Il Doo Chang, Hee Bong Lee
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Publication number: 20130165659Abstract: The present invention relates to a novel method for preparing a compound of formula (2) as the intermediate, which can be effectively used for preparation of a compound of formula (1) exhibiting good inhibitory activity against dipeptidyl peptidase IV enzyme.Type: ApplicationFiled: August 25, 2011Publication date: June 27, 2013Applicant: LG LIFE SCIENCES LTD.Inventors: Bong Chan Kim, Kyu Young Kim, Hee Bong Lee, Ji Eun An, Kyu Woong Lee
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Patent number: 8470836Abstract: Disclosed herein are novel compounds of Formula (1) as defined in the specification having excellent inhibitory activity against dipeptidyl peptidase-IV (DPP-IV), methods of preparing the same and pharmaceutical compositions comprising the same as an active agent.Type: GrantFiled: December 19, 2008Date of Patent: June 25, 2013Assignee: LG Life Sciences, Ltd.Inventors: Chang-Seok Lee, Hyeon Joo Yim, Kyoung-Hee Kim, Jaeick Lee, Sung-Hack Lee, Kyu Woong Lee, Hee Bong Lee, Wan Su Park, Changhee Min
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Patent number: 8410597Abstract: A 3D semiconductor device includes a conductive plate defining four sides and four recesses formed in the four sides, respectively. The conductive plate has first and second surfaces opposite to each other. A plurality of conductive leads are located in the recesses, respectively, and the conductive leads have first and second surfaces opposite to each other. A semiconductor die is attached onto the central area of the conductive plate. A plurality of conductive wires electrically connects the semiconductor die to the conductive leads. An encapsulant encloses, as in a capsule, the conductive plate, the conductive leads, the semiconductor die, and the conductive wires in such a manner that the first and second surfaces of the conductive plate and the first and second surfaces of the conductive leads are exposed to the outside.Type: GrantFiled: October 22, 2009Date of Patent: April 2, 2013Assignee: Hana Micron Inc.Inventors: Hyun Gue Shim, Hee Bong Lee, Jin Wook Jeong
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Publication number: 20120106432Abstract: In one embodiment, after determining downlink backhaul sub-frames based on a constitution period of backhaul sub-frames and determining uplink backhaul sub-frames based on the determined downlink backhaul sub-frames by a relay, all or portions of uplink signals in the determined uplink backhaul sub-frames are transmitted within a backhaul sub-frame allocation period, or after assigning numbers to all of the determined uplink backhaul sub-frames, all or portions of uplink signals are transmitted according to the assigned uplink backhaul sub-frame numbers within a backhaul sub-frame allocation period.Type: ApplicationFiled: January 28, 2011Publication date: May 3, 2012Inventors: Hee Bong LEE, Young Jun Kim, Sang Ha Kim, Byoung-Seong Park, Il Doo Chang, Hong Sup Shin
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Publication number: 20120040704Abstract: The present invention relates to a method for reducing a resource element group (REG) size, which is used at a control channel element (CCE) for a relay physical downlink control channel (R-PDCCH), for the purpose of easy interleaving by a physical resource block (PRB) unit for the R-PDCCH, and a mobile telecommunication system for the same. The mobile telecommunication system of the present invention includes reducing the CCE size to 8 REGs or less of the R-PDCCH to be included in a single PRB.Type: ApplicationFiled: January 28, 2011Publication date: February 16, 2012Inventors: Sang Ha Kim, Hong Sup Shin, Young Jun Kim, Byoung-Seong Park, Il Doo Chang, Hee Bong Lee
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Publication number: 20110243057Abstract: Embodiments for providing a method of controlling timing of a downlink backhaul sub-frame and a relay system for the same are disclosed. According to the present invention, a control signal is transmitted to user equipment during a control symbol period of a sub-frame and a data starting point of the sub-frame is set after a time (SG1) for switching from a transmission mode to a reception mode to receive backhaul data of a base station during a backhaul symbol period. Timing of a transmission sub-frame and a reception sub-frame is delayed by the SG1. A sum of a length of the SG1 and a time (SG2) for switching from the reception mode to the transmission mode is shorter than a length of a symbol having a normal CP. At this time, the lengths of the SG1 and the SG2 are identical to each other or the length of the SG2 is shorter than the length of the SG1. In such a case, the backhaul data are received up to a last symbol period of backhaul symbols of the reception sub-frame.Type: ApplicationFiled: January 28, 2011Publication date: October 6, 2011Inventors: Hong Sup SHIN, Young Jun Kim, Sang Ha Kim, Il Doo Chang, Hee Bong Lee
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Patent number: 7958628Abstract: A vacuum bonding tool method for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.Type: GrantFiled: December 10, 2009Date of Patent: June 14, 2011Assignee: STATS ChipPAC, Ltd.Inventors: Hee-Bong Lee, Hyun-Joon Oh
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Publication number: 20100274013Abstract: Disclosed herein are novel compounds of Formula (1) as defined in the specification having excellent inhibitory activity against dipeptidyl peptidase-IV (DPP-IV), methods of preparing the same and pharmaceutical compositions comprising the same as an active agent.Type: ApplicationFiled: December 19, 2008Publication date: October 28, 2010Applicant: LG LIFE SCIENCES, LTD.Inventors: Chang-Seok Lee, Hyeon Joo Yim, Kyoung-Hee Kim, Jaeick Lee, Sung-Hack Lee, Kyu Woong Lee, Hee Bong Lee, Wan Su Park, Changhee Min
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Publication number: 20100148338Abstract: A 3D semiconductor device includes a conductive plate defining four sides and four recesses formed in the four sides, respectively. The conductive plate has first and second surfaces opposite to each other. A plurality of conductive leads are located in the recesses, respectively, and the conductive leads have first and second surfaces opposite to each other. A semiconductor die is attached onto the central area of the conductive plate. A plurality of conductive wires electrically connects the semiconductor die to the conductive leads. An encapsulant encloses, as in a capsule, the conductive plate, the conductive leads, the semiconductor die, and the conductive wires in such a manner that the first and second surfaces of the conductive plate and the first and second surfaces of the conductive leads are exposed to the outside.Type: ApplicationFiled: October 22, 2009Publication date: June 17, 2010Applicant: HANA MICRON CO., LTD.Inventors: Hyun Gue Shim, Hee Bong Lee, Jin Wook Jeong
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Patent number: 7709946Abstract: A micro USB memory package and method for manufacturing the same, which can meet the USB standard specification, can have a light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof. The micro USB memory package comprises a substrate with a plurality of circuit patterns formed on the top surface thereof, at least one of passive elements connected with the circuit patterns of the substrate, at least one of controllers connected with the circuit patterns of the substrate, at least one of flash memories connected with the circuit patterns of the substrate, and an encapsulation part encapsulating the passive elements, the controllers and the flash memories on the substrate, and at least one of USB lands connected with the circuit patterns by a conducting via are formed on the under surface of one side of the substrate.Type: GrantFiled: October 13, 2006Date of Patent: May 4, 2010Assignee: Hana Micron Co., Ltd.Inventors: Ki Tae Ryu, Nam Young Cho, Yong An Kwon, Hee Bong Lee
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Publication number: 20100083494Abstract: A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.Type: ApplicationFiled: December 10, 2009Publication date: April 8, 2010Applicant: CHIPPAC, INC.Inventors: Hee-Bong Lee, Hyun-Joon Oh
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Patent number: 7650688Abstract: A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.Type: GrantFiled: October 29, 2004Date of Patent: January 26, 2010Assignee: ChipPAC, Inc.Inventors: Hee-Bong Lee, Hyun-Joon Oh
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Publication number: 20070295982Abstract: The present invention relates to a micro USB memory package and a method for manufacturing the same. The object of the present invention is to provide a micro USB memory package and a method for manufacturing the same, which can meet the USB standard specification, can have light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof.Type: ApplicationFiled: October 13, 2006Publication date: December 27, 2007Inventors: Ki Tae Ryu, Nam Young Cho, Yong An Kwon, Hee Bong Lee
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Patent number: 7306971Abstract: Individual pieces of film adhesive (42) are placed on a support surface (46). Diced semiconductor chips (24) are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (52). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (54), to create second chip subassemblies ((56). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (58), to create semiconductor chip packages (60).Type: GrantFiled: October 29, 2004Date of Patent: December 11, 2007Assignee: Chippac Inc.Inventors: Jin-Wook Jeong, In-Sang Yoon, Hee Bong Lee, Hyun-Joon Oh, Hyeog Chan Kwon, Jong Wook Ju, Sang Ho Lee
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Patent number: 7238258Abstract: A system for peeling semiconductor chips from tape is provided with a nose on a housing. The nose has transverse dimensions smaller than the transverse dimensions of a target chip. Apertures are provided through the nose from the housing. Vacuum ports are provided in the housing adjacent the nose. A vacuum source controllably connects to the apertures and the vacuum ports. The nose is positioned adjacent a tape attached on the opposite side thereof to the target chip. Vacuum is applied to attract the tape against the nose and the adjacent portions of the housing to peel the tape from the peripheral edges of the target chip while supporting the tape in the center of the target chip.Type: GrantFiled: April 22, 2005Date of Patent: July 3, 2007Assignee: Stats Chippac Ltd.Inventors: Soo-San Park, Gab-Yong Min, Jin-Wook Jeong, Hee Bong Lee, Jason Lee