Abstract: The present invention relates to an ursodeoxycholic acid-synthetic hydrotalcite-Eudragit hybrid, a pharmaceutical composition containing the same and a method for preparing the same. The ursodeoxycholic acid-synthetic hydrotalcite-Eudragit hybrid according to the present invention is very useful as an active ingredient of a pharmaceutical composition because of its bitter-taste-blocking effect and improved body absorption rate with high solubility.

Abstract: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract: A composition for oral administration of tamsulosin hydrochloride and a controlled release granule formulation comprising the same exhibited excellent stability and sustained release characteristics of tamsulosin hydrochloride regardless of pH changes for an extended period of time.

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and the floating gate. Therefore, inter-cell interference can be reduced without lowering program speed.

Abstract: Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised junction region and the metal wire are connected by a contact plug. Or after a first contact plug of the same area is formed on the junction region up to the bottom of the metal wires, the first contact plug is connected by a second contact plug. Thus, the width of the contact plug except for some portions is increased by maximum. It is thus possible to prevent an electric field from being concentrated and prohibit on-current from reduced, thus improving the electrical properties of devices.

Abstract: Provided is a high voltage transistor in a flash memory device comprising: a source/drain junction of a DDD structure consisting of a high-concentration impurity region and a low-concentration impurity region surrounding the high-concentration impurity region, the high-concentration impurity region being formed in parallel with a gate electrode at a distance spaced by a location in which a contact hole is formed, and having a rectangular shape whose width is the same as or wider than that of the contact hole and whose length is the same as or narrower than that of an active region through which the gate electrode passes. Accordingly, a current density to pass the gate electrode neighboring the contact hole portion and a current density to pass the gate electrode at a portion where the contact hole cannot be formed become uniform. A uniform and constant saturation current can be obtained regardless of the number of the contact hole.

Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and t