Patents by Inventor Hee-Cheol Choi
Hee-Cheol Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105991Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.Type: ApplicationFiled: January 21, 2022Publication date: March 28, 2024Inventors: Min Jung JANG, Min Goo KIM, Young Rok LIM, Ji Young CHOI, Sang Ho LEE, Wan Chul KANG, Jong Cheol YUN, Ji Seong HAN, Hee Jeong RYU, Jae Won CHUNG
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Publication number: 20240097188Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.Type: ApplicationFiled: January 21, 2022Publication date: March 21, 2024Inventors: Min Jung JANG, Min Goo KIM, Young Rok LIM, Ji Young CHOI, Sang Ho LEE, Wan Chul KANG, Jong Cheol YUN, Ji Seong HAN, Hee Jeong RYU, Jae Won CHUNG
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Publication number: 20240097190Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.Type: ApplicationFiled: January 21, 2022Publication date: March 21, 2024Inventors: Min Jung JANG, Min Goo KIM, Young Rok LIM, Ji Young CHOI, Sang Ho LEE, Wan Chul KANG, Jong Cheol YUN, Ji Seong HAN, Hee Jeong RYU, Jae Won CHUNG
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Publication number: 20240097189Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.Type: ApplicationFiled: January 21, 2022Publication date: March 21, 2024Inventors: Min Jung JANG, Min Goo KIM, Young Rok LIM, Ji Young CHOI, Sang Ho LEE, Wan Chul KANG, Jong Cheol YUN, Ji Seong HAN, Hee Jeong RYU, Jae Won CHUNG
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Patent number: 8854244Abstract: An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.Type: GrantFiled: August 30, 2013Date of Patent: October 7, 2014Assignee: Aptina Imaging CorporationInventors: Hong-Joo Park, Sanghoon Lim, Hee-Cheol Choi, Hai Yan
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Publication number: 20140078360Abstract: An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.Type: ApplicationFiled: August 30, 2013Publication date: March 20, 2014Applicant: Aptina Imaging CorporationInventors: Hong-Joo Park, Sanghoon Lim, Hee-Cheol Choi, Hai Yan
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Patent number: 7560796Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.Type: GrantFiled: December 6, 2006Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Seok Shin, Hee-Cheol Choi, Seung-Hoon Lee, Kyung-Hoon Lee, Young-Jae Cho
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Publication number: 20090128231Abstract: A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current.Type: ApplicationFiled: January 14, 2009Publication date: May 21, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hee-Cheol Choi
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Patent number: 7508427Abstract: A system and method for processing an input signal, such as an analog video input signal, are described. The system includes a correlated double sampler (CDS) for receiving an input signal, sampling the input signal and providing an output signal, the CDS comprising an amplifier for amplifying the input signal. The sampled and amplified output of the CDS is applied to a programmable gain amplifier (PGA). The PGA receives the output signal from the CDS and amplifies the received signal. By providing gain in both the CDS and the PGA, the system of the invention uses much smaller area than conventional systems. Also, a pseudo log scale gain response for the overall system is realized.Type: GrantFiled: April 14, 2004Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hee-Cheol Choi
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Patent number: 7495507Abstract: A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current.Type: GrantFiled: August 23, 2006Date of Patent: February 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hee-Cheol Choi
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Publication number: 20070138587Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.Type: ApplicationFiled: December 6, 2006Publication date: June 21, 2007Inventors: Eun-Seok Shin, Hee-Cheol Choi, Seung-Hoon Lee, Kyung-Hoon Lee, Young-Jae Cho
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Publication number: 20070057717Abstract: A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current.Type: ApplicationFiled: August 23, 2006Publication date: March 15, 2007Inventor: Hee-Cheol Choi
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Patent number: 6891494Abstract: The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2n ?Ivoltages and being arranged to be folded; a comparator array including (2n?1) comparators for comparing voltage differences between the respective 2n ?Ivoltages and an analog input signal to generate a digital thermometer code having (2n?1) bits and an encoder for encoding the digital thermometer code having (2n?1) bits to generate an n-bit digital signal.Type: GrantFiled: October 16, 2003Date of Patent: May 10, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Hee-Cheol Choi
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Publication number: 20050018061Abstract: A system and method for processing an input signal, such as an analog video input signal, are described. The system includes a correlated double sampler (CDS) for receiving an input signal, sampling the input signal and providing an output signal, the CDS comprising an amplifier for amplifying the input signal. The sampled and amplified output of the CDS is applied to a programmable gain amplifier (PGA). The PGA receives the output signal from the CDS and amplifies the received signal. By providing gain in both the CDS and the PGA, the system of the invention uses much smaller area than conventional systems. Also, a pseudo log scale gain response for the overall system is realized.Type: ApplicationFiled: April 14, 2004Publication date: January 27, 2005Inventor: Hee-Cheol Choi
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Publication number: 20040080445Abstract: The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2n voltages and being arranged to be folded; a comparator array including (2n−1) comparators for comparing voltage differences between the respective 2n number of voltages and an analog input signal to generate a digital signal having (2n−1) thermometer codes; and an encoder for encoding the digital signal having (2n−1) thermometer codes to generate an n-bit digital signal.Type: ApplicationFiled: October 16, 2003Publication date: April 29, 2004Applicant: Samsung Electronics Co., Ltd.Inventor: Hee-Cheol Choi
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Patent number: 6597235Abstract: A boost circuit, such as might be used to generate a boosted voltage in an integrated circuit device (e.g., an EEPROM), includes a plurality of charge pump circuits having outputs connected in common and that generate current pulses responsive to respective phased periodic signals. The boost circuit further includes a multi-phase periodic signal generator circuit that generates the phased periodic signals such that they have respective different phases. For example, the multi-phase periodic signal generator circuit may include a control signal generator circuit that produces a control signal responsive to a voltage produced by the plurality of charge pump circuits, and an oscillator circuit that generates the plurality of phased periodic signals responsive to the control signal. Related operating methods are described.Type: GrantFiled: January 9, 2002Date of Patent: July 22, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Hee-cheol Choi
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Publication number: 20020101277Abstract: A boost circuit, such as might be used to generate a boosted voltage in an integrated circuit device (e.g., an EEPROM), includes a plurality of charge pump circuits having outputs connected in common and that generate current pulses responsive to respective phased periodic signals. The boost circuit further includes a multi-phase periodic signal generator circuit that generates the phased periodic signals such that they have respective different phases. For example, the multi-phase input signal generator circuit may include a control signal generator circuit that produces a control signal responsive to a voltage produced by the plurality of charge pump circuits, and an oscillator circuit that generates the plurality of phased periodic signals responsive to the control signal. Related operating methods are described.Type: ApplicationFiled: January 9, 2002Publication date: August 1, 2002Inventor: Hee-Cheol Choi
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Patent number: 6259392Abstract: Multiplying Digital-to-Analog Converters (MDAC) multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal to produce an analog output signal at an output terminal. The MDACs include unit capacitors and a feedback capacitor. The unit capacitors are connected to the analog input terminal during a first time interval and the unit capacitors are selectively connected to a first reference voltage, a second reference voltage or the output terminal during a second time interval in response to the digital input signal at the digital input terminal. The feedback capacitor is connected to the second reference voltage during the first time interval and to the output terminal during the second time interval.Type: GrantFiled: October 6, 1998Date of Patent: July 10, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Cheol Choi, Kwang-Hee Lee
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Patent number: 6052025Abstract: Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.Type: GrantFiled: July 29, 1998Date of Patent: April 18, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Young Chang, You-Mi Lee, Seung-Hoon Lee, Geun-Soon Kang, Hee-Cheol Choi
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Patent number: 5952952Abstract: A binary-weighted capacitor array is applicable for use in analog-to-digital or digital-to-analog converters, switched-capacitor filters, etc. A plurality of unit capacitors are arranged in a lateral row. The row is laid out in parallel to a switch array so that each metal interconnect between a unit capacitor and a corresponding switch is of a uniform length. This layout eliminates several limitations commonly found in capacitor arrays, including: top-plate parasitic error due to metal interconnections and metal overlap; ratio error due to oxide thickness gradients; and edge-definition errors.Type: GrantFiled: June 16, 1998Date of Patent: September 14, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Cheol Choi, Geun-Soon Kang