Abstract: Certain aspects of the present disclosure provide techniques for transceiver timing controls in a synchronized network. A method that may be performed by a user equipment (UE) or a base station (BS) includes determining a first instance of time corresponding to a beginning of a wireless transmission of data by a transceiver, determining a second instance of time corresponding to a beginning of a process configured to load a plurality of buffers with a portion of the data, loading of the plurality of buffers with the data, and transmitting, the data at the first instance of time.

Abstract: Techniques for writing to registers associated with MIMO signal paths are disclosed. In an embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

Abstract: A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.

Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.

Abstract: Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions.

Abstract: Techniques for writing to registers associated with MIMO signal paths are disclosed. In are embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

Abstract: An n-dimensional broken mesh network in which input output protocol processing block is connected to a broken link and external traffic link is connected to the input output protocol processing block. Broken link is formed by breaking connection between a starting switching element and an ending switching element of each dimension in mesh network.

Abstract: A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.

Abstract: Disclosed is a multi-stage (NXN) interconnection network which has N input ports and N output ports, for transmitting packets from the input ports to the output ports. The network comprises a multi-stage packet switching network having at least logMN switching stages; and each of the switching stages having N/2 MXM switching elements, where M is the number of input or output ports of each switching element. Each switching element at each stage comprises X bypassing input ports, M−X input routing ports, X bypassing output ports and M−X output routing ports, where X is 1 or integer of more than 1. The bypassing output ports of each switching element at each stage are connected to bypassing input ports of each of switching elements which are disposed in a same position of a next stage, respectively, and the output routing ports of each switching element at each stage are connected to input routing ports of each of the switching elements at the next stage by means of perfect shuffle connection.