Abstract: Integrated circuit memory devices having improved burst mode operation include an array of memory cells arranged as a plurality of normal rows of memory cells electrically coupled to respective normal section word lines (SWL) and a plurality of redundant rows of memory cells electrically coupled to respective redundant section word lines (RSWL). A first normal section row decoder is also provided. The first normal section row decoder has first inputs electrically coupled to a plurality of burst address selection lines (Ci, Cj, Ck and Cl), a second input electrically coupled to a normal main word line (MWL) and outputs electrically coupled to a plurality of the normal section word lines (SWL1-4). A first redundancy section row decoder is also preferably provided.