Abstract: A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.

Abstract: A method of reserving access to a shared communication link by a number of devices is disclosed, having the steps of: (1) assigning a plurality, m, of counters to each of the number of devices, each counter counting from a first count value to a second count value; (2) using the values within the counting range from the first count value to the second count value to uniquely identify each of the number of devices; and (3) pausing the counting operation of a first counter of the plurality of counters, in each of the number of devices, that has the count value identifying a first of the number of devices requesting access to the shared communication link. Also disclosed, is an apparatus that supports the above-described method.

Abstract: A semiconductor memory device conserves chip area by jointly connecting transistors which are respectively connected to pads adjacent to each other. The device includes first and second electrostatic discharge protection MOSFET transistors which have drains respectively connected to pads adjacent to each other and which define a first active area. A common source is arranged between the first and second transistors areas and defines a second active area in common to both transistors. The device is connected to a single power supply at the gates and sources thereof. The transistors also share common active ground lines.

Abstract: A level shifter and a data output buffer adapted for use in a semiconductor memory device including a memory cell for storing data, a sense amplifier for amplifying data read from the memory cell and generating an ECL-level output signal, and a level shifter for converting the ECL-level output signals into a CMOS-level signal, wherein the level shifter has a level shifting means receiving the ECL-level data signals, converting the input data to CMOS-levels, and outputting a result, and a delay for delaying the result so as to control its current consumption of the level shifter.