Patents by Inventor Hee Do Na
Hee Do Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12764950Abstract: A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.Type: GrantFiled: December 19, 2023Date of Patent: October 13, 2026Assignee: SK hynix Inc.Inventors: Hee Do Na, Hee Soo Kim, Yoon Soo Oh, Chang Soo Lee, Chul Young Ham
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Publication number: 20260089956Abstract: The technology relates to a semiconductor device and a method for manufacturing the semiconductor device. According to the technology, a method for manufacturing a semiconductor device may comprise forming a gapfill target structure on a semiconductor substrate, the gapfill target structure including a horizontal recess parallel with the semiconductor substrate and having a first surface and a vertical slit extending from the horizontal recess and having a second surface perpendicular to the semiconductor substrate, removing a native oxide from the first surface to form a pre-cleaned first surface, forming, in-situ, a first semiconductor material on the pre-cleaned first surface and forming a second semiconductor material on the first semiconductor material.Type: ApplicationFiled: December 3, 2025Publication date: March 26, 2026Applicant: SK hynix Inc.Inventors: Hee Do NA, Sun Kak HWANG, Sung Soon KIM
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Publication number: 20250185335Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.Type: ApplicationFiled: February 4, 2025Publication date: June 5, 2025Applicant: SK hynix Inc.Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
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Patent number: 12255237Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.Type: GrantFiled: September 15, 2023Date of Patent: March 18, 2025Assignee: SK hynix Inc.Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
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Publication number: 20250081452Abstract: A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.Type: ApplicationFiled: December 19, 2023Publication date: March 6, 2025Inventors: Hee Do NA, Hee Soo KIM, Yoon Soo OH, Chang Soo LEE, Chul Young HAM
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Publication number: 20240006495Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Applicant: SK hynix Inc.Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
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Patent number: 11799003Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.Type: GrantFiled: April 15, 2021Date of Patent: October 24, 2023Assignee: SK hynix Inc.Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
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Publication number: 20220181455Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.Type: ApplicationFiled: April 15, 2021Publication date: June 9, 2022Applicant: SK hynix Inc.Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
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Publication number: 20220123015Abstract: The technology relates to a semiconductor device and a method for manufacturing the semiconductor device. According to the technology, a method for manufacturing a semiconductor device may comprise forming a gapfill target structure on a semiconductor substrate, the gapfill target structure including a horizontal recess parallel with the semiconductor substrate and having a first surface and a vertical slit extending from the horizontal recess and having a second surface perpendicular to the semiconductor substrate, removing a native oxide from the first surface to form a pre-cleaned first surface, forming, in-situ, a first semiconductor material on the pre-cleaned first surface and forming a second semiconductor material on the first semiconductor material.Type: ApplicationFiled: August 25, 2021Publication date: April 21, 2022Applicant: SK hynix Inc.Inventors: Hee Do NA, Sun Kak HWANG, Sung Soon KIM
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Patent number: 10243000Abstract: Provided are a 3-dimensional non-volatile memory device and a method of fabricating the same. The 3-dimensional non-volatile memory device may include a substrate; semiconductor pillars, which are arranged at a certain interval in a first direction and a second direction different from the first direction; a string isolation film, which is arranged between the semiconductor pillars arranged in the first direction among the semiconductor pillars and extends in the first direction and a third direction vertical to the main surface of the substrate; first sub-electrodes repeatedly stacked on the substrate in the third direction; second sub-electrodes, which are electrically isolated from the first sub-electrodes by the string isolation film, and are repeatedly stacked on the substrate in the third direction; and information storage films including a first information storage film and a second information storage film.Type: GrantFiled: May 18, 2017Date of Patent: March 26, 2019Assignee: UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITYInventors: Hyun Chul Sohn, Hee Do Na, Young Mo Kim
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Publication number: 20170338243Abstract: Provided are a 3-dimensional non-volatile memory device and a method of fabricating the same. The 3-dimensional non-volatile memory device may include a substrate; semiconductor pillars, which are arranged at a certain interval in a first direction and a second direction different from the first direction; a string isolation film, which is arranged between the semiconductor pillars arranged in the first direction among the semiconductor pillars and extends in the first direction and a third direction vertical to the main surface of the substrate; first sub-electrodes repeatedly stacked on the substrate in the third direction; second sub-electrodes, which are electrically isolated from the first sub-electrodes by the string isolation film, and are repeatedly stacked on the substrate in the third direction; and information storage films including a first information storage film and a second information storage film.Type: ApplicationFiled: May 18, 2017Publication date: November 23, 2017Inventors: Hyun Chul Sohn, Hee Do Na, Young Mo Kim
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Patent number: 9159754Abstract: An image sensor includes a pixel layer in which an active pixel array and an optical black pixel array are formed; a first anti-reflective layer which is formed over the active pixel array, and including a hafnium oxide layer with a high transmittance; and a second anti-reflective layer which is formed over the optical black pixel array, and including a hafnium oxide layer with a low transmittance.Type: GrantFiled: December 22, 2014Date of Patent: October 13, 2015Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Do Hwan Kim, Hyun Chul Sohn, Hee Do Na, Kyung Dong Yoo, Jong Chae Kim