Patents by Inventor Hee Hwan JI

Hee Hwan JI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12356727
    Abstract: A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: July 8, 2025
    Assignee: SK keyfoundry Inc.
    Inventor: Hee Hwan Ji
  • Patent number: 12224211
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 11, 2025
    Assignee: SK keyfoundry Inc.
    Inventors: Hee Hwan Ji, Ji Man Kim, Song Hwa Hong, Bo Seok Oh
  • Patent number: 12159806
    Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: December 3, 2024
    Assignee: SK keyfoundry Inc.
    Inventors: Ji Man Kim, Hee Hwan Ji, Song Hwa Hong
  • Publication number: 20240243132
    Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 18, 2024
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Ji Man KIM, Hee Hwan JI, Song Hwa HONG
  • Patent number: 11923368
    Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Ji Man Kim, Hee Hwan Ji, Song Hwa Hong
  • Publication number: 20230023179
    Abstract: A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.
    Type: Application
    Filed: December 28, 2021
    Publication date: January 26, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hee Hwan JI
  • Publication number: 20220399332
    Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.
    Type: Application
    Filed: December 17, 2021
    Publication date: December 15, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Ji Man KIM, Hee Hwan JI, Song Hwa HONG
  • Publication number: 20220277960
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Key Foundry Co., Ltd.
    Inventors: Hee Hwan JI, Ji Man KIM, Song Hwa HONG, Bo Seok OH
  • Patent number: 11373872
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 28, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Hee Hwan Ji, Ji Man Kim, Song Hwa Hong, Bo Seok Oh
  • Patent number: 11133414
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: September 28, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
  • Publication number: 20210272811
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 2, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Hee Hwan JI, Ji Man KIM, Song Hwa HONG, Bo Seok OH
  • Patent number: 10985192
    Abstract: A display driver semiconductor device includes a high voltage well region formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer formed using a deposition process. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer formed using a thermal process. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 20, 2021
    Assignee: KEY FOUNDRY., LTD.
    Inventors: Bo Seok Oh, Hee Hwan Ji, Kwang Ho Park
  • Patent number: 10763800
    Abstract: A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 1, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Hee Hwan Ji, Tae Ho Kim
  • Publication number: 20200251592
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Application
    Filed: April 17, 2020
    Publication date: August 6, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jae Hyung JANG, Jin Yeong SON, Hee Hwan JI
  • Patent number: 10700198
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
  • Patent number: 10686071
    Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 16, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
  • Patent number: 10637467
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
  • Publication number: 20200066759
    Abstract: A display driver semiconductor device includes a high voltage well region formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer formed using a deposition process. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer formed using a thermal process. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer.
    Type: Application
    Filed: October 29, 2019
    Publication date: February 27, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Bo Seok OH, Hee Hwan JI, Kwang Ho PARK
  • Patent number: 10504932
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 10, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
  • Publication number: 20190229685
    Abstract: A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 25, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Hee Hwan JI, Tae Ho KIM