Abstract: Exposure equipment having a wafer pre-alignment apparatus and a wafer pre-alignment method using the same reduce wafer pre-alignment errors. The exposure equipment comprises a plurality of exposure units in which lots of wafers are loaded, respectively, and a central control unit. The exposure units are constituted by an alignment apparatus that can detect the relative angular orientation of each wafer transferred to the apparatus and thus, sense any misalignment of the wafers. The central control unit calculates inherent error values for the exposure units based on data transmitted to the central control unit from the alignment apparatus. The central control unit also controls the equipment based on the inherent error values of the exposure units to compensate for the misalignment of the wafers in the exposure units.

Abstract: A plasma display device includes a PDP including discharge cells, address electrodes extending in a first direction and corresponding to the discharge cells, and sustain electrodes and scan electrodes in parallel with each other and crossing the address electrodes in the discharge cells, the sustain electrodes including first terminals and the scan electrodes including second terminals, a chassis base supporting PDP, an integrated board on the chassis base, the chassis base being between the integrated board and the PDP, and an integrated flexible circuit connecting the integrated board to the first terminals of the sustain electrodes and to the second terminals of the scan electrodes, the first terminals of the sustain electrodes and second terminals of the scan electrodes being arranged at a first side of four sides of the PDP.

Abstract: A soft start circuit is connected to a pulse width modulation controller including an oscillator, and a functionality of modulating amplitude to a pulse width and a power supply includes the soft start circuit. The soft start circuit includes a frequency controlling unit, a duty ratio establishing unit, and a variable switching unit. The frequency controlling unit generates first and second parameter signals for determining a frequency signal frequency by a power source from the PWM controller and provides them to the PWM controller. The duty ratio establishing unit generates a third parameter for determining amplitude of the frequency signal generated by the PWM controller according to a reference voltage, and provides it to the PWM controller. The variable switching unit determines whether it is a first predetermined time from a start-up state, and controls the first parameter of the frequency controller during the first predetermined time.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A soft start circuit is connected to a pulse width modulation controller including an oscillator, and a functionality of modulating amplitude to a pulse width and a power supply includes the soft start circuit. The soft start circuit includes a frequency controlling unit, a duty ratio establishing unit, and a variable switching unit. The frequency controlling unit generates first and second parameter signals for determining a frequency signal frequency by a power source from the PWM controller and provides them to the PWM controller. The duty ratio establishing unit generates a third parameter for determining amplitude of the frequency signal generated by the PWM controller according to a reference voltage, and provides it to the PWM controller. The variable switching unit determines whether it is a first predetermined time from a start-up state, and controls the first parameter of the frequency controller during the first predetermined time.

Abstract: A PDP having a driving circuit that reduces the reset voltage of the PDP driving waveforms to make it possible to use low-voltage elements and to achieve high contrasts is disclosed. Since conventional PDP waveforms require very high reset voltages, it causes a problem of intense background light emissions, low contrasts, use of high-voltage components, and increased circuit costs. According to the driving waveforms of the present invention, relative voltage differences between the address electrode and the X electrode and between the X electrode and the Y electrode are considered to design waveforms of low reset voltages, thereby providing high contrasts and low-cost circuit.

Abstract: An asymmetrical DC to DC converter using one or more NAND gates. In one embodiment, an asymmetrical DC to DC converter includes a converter unit including a switching unit and adapted to transform a first voltage having a first level to a second voltage having a second level according to a switching operation of the switching unit and an output voltage control unit including at least one NAND gate and adapted to control the second level of the second voltage to be substantially uniform. The output voltage control unit is further adapted to generate a driving signal for the switching unit via the at least one NAND gate. As such, an asymmetrical control circuit that is suitable for an asymmetrical half bridge converter or an active clamp converter can be simply and inexpensively realized using a NAND gate instead of using expensive dedicated chips.

Abstract: Exposure equipment having a wafer pre-alignment apparatus and a wafer pre-alignment method using the same reduce wafer pre-alignment errors. The exposure equipment comprises a plurality of exposure units in which lots of wafers are loaded, respectively, and a central control unit. The exposure units are constituted by an alignment apparatus that can detect the relative angular orientation of each wafer transferred to the apparatus and thus, sense any misalignment of the wafers. The central control unit calculates inherent error values for the exposure units based on data transmitted to the central control unit from the alignment apparatus. The central control unit also controls the equipment based on the inherent error values of the exposure units to compensate for the misalignment of the wafers in the exposure units.

Abstract: A PDP driving method that reduces the reset voltage of the PDP driving waveforms to make it possible to use low-voltage elements and to achieve high contrasts is disclosed. Since conventional PDP waveforms require very high reset voltages, it causes a problem of intense background light emissions, low contrasts, use of high-voltage components, and increased circuit costs. According to the driving waveforms of the present invention, relative voltage differences between the address electrode and the X electrode and between the X electrode and the Y electrode are considered to design waveforms of low reset voltages, thereby providing high contrasts and low-cost circuit.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A plasma display panel sustain-discharge circuit. First and second signal lines for supplying first and second voltages and at least one inductor coupled between one end of the panel capacitor and a third voltage are formed. Energy is stored in the inductor through a path formed between the third voltage and the first signal line in a state where a voltage of one end of the panel capacitor is substantially fixed to the first voltage. The voltage of one end of the panel capacitor substantially decreases to the second voltage using resonance current generated between the inductor and the panel capacitor and the stored energy. Energy is stored in the inductor through a path formed between the third voltage and the second line in a state where a voltage of one end of the panel capacitor is substantially fixed to the second voltage.

Abstract: A PDP driving method that reduces the reset voltage of the PDP driving waveforms to make it possible to use low-voltage elements and to achieve high contrasts is disclosed. Since conventional PDP waveforms require very high reset voltages, it causes a problem of intense background light emissions, low contrasts, use of high-voltage components, and increased circuit costs. According to the driving waveforms of the present invention, relative voltage differences between the address electrode and the X electrode and between the X electrode and the Y electrode are considered to design waveforms of low reset voltages, thereby providing high contrasts and low-cost circuit.

Abstract: A plasma display panel including a plurality of address electrodes, a plurality of scan electrodes, and a plurality of sustain electrodes, and an energy recovery circuit (ERC) timing control method thereof. The plasma display panel includes a plasma panel, a controller, an address electrode driver, a sustain electrode driver, and a scan electrode driver. A load ratio is determined from an image signal. The ERC timing is determined corresponding to the load ratio or the automatic power control level corresponding to the load ratio. The sustain electrodes and the scan electrodes operate in response to the determined ERC timing.

Abstract: A PDP having a driving circuit that reduces the reset voltage of the PDP driving waveforms to make it possible to use low-voltage elements and to achieve high contrasts is disclosed. Since conventional PDP waveforms require very high reset voltages, it causes a problem of intense background light emissions, low contrasts, use of high-voltage components, and increased circuit costs. According to the driving waveforms of the present invention, relative voltage differences between the address electrode and the X electrode and between the X electrode and the Y electrode are considered to design waveforms of low reset voltages, thereby providing high contrasts and low-cost circuit.

Abstract: A PDP driving method that reduces the reset voltage of the PDP driving waveforms to make it possible to use low-voltage elements and to achieve high contrasts is disclosed. Since conventional PDP waveforms require very high reset voltages, it causes a problem of intense background light emissions, low contrasts, use of high-voltage components, and increased circuit costs. According to the driving waveforms of the present invention, relative voltage differences between the address electrode and the X electrode and between the X electrode and the Y electrode are considered to design waveforms of low reset voltages, thereby providing high contrasts and low-cost circuit.

Abstract: A method of driving a plasma display panel having front and rear substrates disposed opposite each other, parallel X and Y electrode lines formed between the front and rear substrates, and address electrode lines formed orthogonal to the X and Y electrode lines to define corresponding discharge cells at interconnections, the X electrode lines are in X groups, and the Y electrode lines are in Y groups, where no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups. The X and Y electrode lines of the respective X and Y groups are commonly connected to be driven, and at least first and second subfields are driven in an overlapping manner for displaying gray scales during a unit display period. The method includes a scan step, an address step, a display step, a second driving step, and a repetition step.

Abstract: A resetting method includes a line discharge step, an erasure step, and an iteration step. The line discharge step is performed during a part of a first pulse width period. During the first pulse width period since a second subfield corresponding to a first XY-electrode line pair starts after a first subfield corresponding to the first XY-electrode line pair ends, a negative voltage of a first level is applied to all X-electrode lines, and simultaneously, a positive voltage of the first level is applied to all Y-electrode lines. In the line discharge step, a negative voltage of a second level higher than the first level is applied to an X-electrode line of the first XY-electrode line pair, and simultaneously, a positive voltage of a third level higher than the first level is applied to a Y-electrode line of the first XY-electrode line pair, thereby provoking discharges in all discharge cells corresponding to the first XY-electrode line pair.