Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

Abstract: A storage device includes nonvolatile memories and a device controller configured to store data being received from an external device in an internal RAM, according to a command and an address being received from the external device. The device controller controls the nonvolatile memories according to the data stored in the internal RAM, distinguishes whether phase bits received with the data and also stored in the internal RAM are valid, and processes the data stored in the internal RAM when the phase bits are valid.

Abstract: An access method of a storage device including heterogeneous nonvolatile memories includes receiving write-requested data; and writing the data in a first memory device or a second memory device based on a characteristic of the data, wherein the first memory device is capable of performing an overwrite operation and the second memory device is incapable of performing the overwrite operation.

Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command.

Abstract: A storage device includes nonvolatile memories and a device controller configured to store data being received from an external device in an internal RAM, according to a command and an address being received from the external device. The device controller controls the nonvolatile memories according to the data stored in the internal RAM, distinguishes whether phase bits received with the data and also stored in the internal RAM are valid, and processes the data stored in the internal RAM when the phase bits are valid.

Abstract: Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.

Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.