Abstract: The present disclosure relates to a nanostructure for detecting viruses including an amphipathic polymer, and a diagnostic platform using the same, wherein the nanostructure is capable of specifically detecting viruses through silica-based nanoparticles with excellent stability and high dispersion and a biocompatible amphipathic polymer, such that it is possible to develop a diagnostic platform with high sensitivity through binding and agglomeration of the nanostructure and viruses and enable rapid and accurate diagnosis of a target virus.

Abstract: The present invention relates to use of a compound of chemical formula 1 or a pharmaceutically acceptable salt thereof as a selective agonist of the melanocortin-4-receptor (MC4R).

Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.

Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.

Abstract: A method for producing high-concentration stem cell exosomes with enhanced anti-inflammatory function using Lipopolysaccharide (LPS) and/or Lipoteichoic Acid (LTA), as well as anti-inflammatory and/or regenerative compositions that can be produced by the aforementioned method are disclosed. The production method for the anti-inflammatory composition includes a first step of treating stem cells during cultivation with one or more selected from a group consisting of Lipopolysaccharide (LPS) and Lipoteichoic Acid (LTA), and optionally, a second step of separating stem cells, their culture medium, and/or their exosomes obtained as a result of the first step.

Abstract: A method for isolating and culturing umbilical cord blood stem cells that express high levels of GDF-3 is disclosed. Umbilical cord blood stem cells isolated and cultured as described herein exhibit high expression of GDF-3. Stem cells with high expression of GDF-3 maintain high proliferation capacity contrary to conventional stem cells even as passages progress, allowing for the advantage of obtaining a large quantity of healthy stem cells. Furthermore, due to the higher proliferation rate of stem cells, it has been observed that the concentration of extracellular matrix components secreted by the cells is also higher. Therefore, when utilizing GDF-3 high-expressing umbilical cord blood stem cells for the production of cell and culture medium compositions, it is possible to produce raw materials with excellent efficacy and effects.

Abstract: The present invention relates to a method for preparing a culture medium containing exosomes released by umbilical cord blood stem cells. The preparation method is based on culturing the umbilical cord blood stem cells in a serum-free medium supplemented with GDF-11, EGF, FGF2, TFG-?1, and/or VEGF. The culture medium produced by treating umbilical cord blood stem cells with a serum-free medium supplemented with 5 types of growth factors and the exosomes isolated from the culture medium has a higher total protein content and extracellular matrix protein content, when compared to a culture medium produced by culturing umbilical cord blood stem cells in a serum-free medium to which the growth factor is not added. In addition, exosomes released by umbilical cord blood stem cells cultured in a serum-free medium containing five growth factors have a high concentration, a small size, and an even distribution.

Abstract: Provided are a method of preparing induced pluripotent stem cells (iPSCs) and embryonic stem cells (ESCs), both having a reduced expression level of HLA, which is a cause of immune rejection upon transplantation of cells, tissues, or organs, a method of preparing mesenchynmal stem cells (MSCs) by using a novel differentiation method of iPSCs, and a cell therapy product using the iPSCs, ESCs, and/or MSCs. The HLA gene-deleted MSCs prepared in the present invention may be used to prepare various types of cells that do not cause immune rejection, and may be used for therapeutic purposes in the future.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Abstract: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

Abstract: A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract: A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract: A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Abstract: Provided is a technique for improving the transfer latency of vector register file data when an interrupt is generated. According to an aspect, when interrupt occurs, a core determines whether to store vector register file data currently being executed in a first memory or in a second memory based on whether or not the first memory can store the vector register file data therein. In response to not being able to store the vector register file data in the first memory, a data transfer unit, which is implemented as hardware, is provided to store vector register file data in the second memory.

Abstract: A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.