Abstract: A semiconductor device includes first and second memory regions spaced apart from each other and a fail information storage region disposed between the first and second memory regions. A parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region. The parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region. An error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region. The error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region.

Abstract: A semiconductor device includes first and second memory regions spaced apart from each other and a fail information storage region disposed between the first and second memory regions. A parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region. The parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region. An error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region. The error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region.

Abstract: A memory device includes a memory region, and a setting circuit suitable for changing setting information based on a temperature information signal so that the memory region operates according to a first condition at pseudo cryogenic temperature, and operates according to a second condition at room temperature.

Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.

Abstract: A semiconductor device includes a mode setting circuit configured to allocate any one of values to a mode signal based on an event signal, an address converter configured to generate a conversion address by converting at least one address based on the mode signal, and a memory circuit configured to perform an operation corresponding to the conversion address.

Abstract: A semiconductor device includes a mode setting circuit configured to allocate any one of values to a mode signal based on an event signal, an address converter configured to generate a conversion address by converting at least one address based on the mode signal, and a memory circuit configured to perform an operation corresponding to the conversion address.

Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.

Abstract: A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.

Abstract: A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

Abstract: A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving blocks configured to transfer data received from global input/output lines to the pad blocks in response to a read operation, and transfer data from the pad blocks to the global input/output lines in response to a write operation. The input/output driving blocks are disposed in a peripheral region and control a width of the data.

Abstract: A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.

Abstract: A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.

Abstract: A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. The buffering section configured to generate a delayed strobe signal from the strobe signal while the division enable signal is enabled. The strobe signal driving section configured to generate a plurality of data strobe signals with a larger pulse width than the delayed strobe signal, in response to the division enable signal and the delayed strobe signal.

Abstract: A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving blocks configured to transfer data received from global input/output lines to the pad blocks in response to a read operation, and transfer data from the pad blocks to the global input/output lines in response to a write operation. The input/output driving blocks are disposed in a peripheral region and control a width of the data.

Abstract: A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.

Abstract: A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

Abstract: A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. The buffering section configured to generate a delayed strobe signal from the strobe signal while the division enable signal is enabled. The strobe signal driving section configured to generate a plurality of data strobe signals with a larger pulse width than the delayed strobe signal, in response to the division enable signal and the delayed strobe signal.