Abstract: The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure, it is possible to produce an organic electroluminescent device having improved driving voltage, power efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.

Abstract: An air conditioning device for a vehicle includes: a housing having an inside divided into an inflow space, a heat exchange space, and an outflow space, which are straightly arranged, and having a plurality of discharge ports, which communicates with an interior, at the inflow space; a blowing unit disposed at the inflow space of the housing and configured to blow air; a heat exchange unit disposed at the heat exchange space of the housing and configured to adjust a temperature of conditioned air by exchanging heat with air; and an opening-closing door disposed at the outflow space of the housing and configured to open and close the plurality of discharge ports such that conditioned air at an adjusted temperature selectively flows to the plurality of discharge ports. The air conditioning device adjusts the temperature of conditioned air for respective modes and reduces a flow resistance of air.

Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Abstract: An indoor live ammunition shooting range facility system includes a ventilation facility installed in an indoor live ammunition shooting range, and configured to ventilate air of the indoor live ammunition shooting range; a targeting device facility installed in the indoor live ammunition shooting range, and configured to provide a shooting target; a bulletproof facility installed to protect components exposed to an inside of the indoor live ammunition shooting range among components configuring the ventilation facility and the target device facility and to protect a wall surface of the indoor live ammunition shooting range; a bullet head recovery facility installed on a side opposite to a shooting position, and configured to recover a bullet head; and a control facility installed in the indoor live ammunition shooting range, and configured to control the ventilation facility, the target device facility and the bullet head recovery facility.

Abstract: An electronic device may have an antenna that conveys radio-frequency signals at frequencies greater than 10 GHz. The antenna may be embedded in a substrate. The substrate may have routing layers, first antenna layers on the routing layers, second antenna layers on the first antenna layers, and a third antenna layers on the second antenna layers. The antenna may include first traces on the first antenna layers, second traces on the second antenna layers, and third traces on the third antenna layers. The first antenna layers may have a first bulk dielectric permittivity. The second layers may have a second bulk dielectric permittivity. The third layers may have a third bulk dielectric permittivity. At least one of the first, second, and third bulk dielectric permittivities may be different from the others. This may differentially load the antenna across the antenna layers, thereby broadening the bandwidth of the antenna.

Abstract: An electronic device may have an antenna that conveys radio-frequency signals at frequencies greater than 10 GHz. The antenna may be embedded in a substrate. The substrate may have routing layers, first antenna layers on the routing layers, second antenna layers on the first antenna layers, and a third antenna layers on the second antenna layers. The antenna may include first traces on the first antenna layers, second traces on the second antenna layers, and third traces on the third antenna layers. The first antenna layers may have a first bulk dielectric permittivity. The second layers may have a second bulk dielectric permittivity. The third layers may have a third bulk dielectric permittivity. At least one of the first, second, and third bulk dielectric permittivities may be different from the others. This may differentially load the antenna across the antenna layers, thereby broadening the bandwidth of the antenna.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: The present invention provides a bullet collecting box which is installed with a plurality of rubber plates in the bullet collecting box having a rectangular parallelepiped shape and filled with rubber powder filling materials having a particle size of 0.1 to 3 mm therein, thereby collecting the bullets fired in the indoor shooting range without damage, and a bullet collecting system which can be used by installing the bullet collecting box in the indoor shooting range. Also, the present invention provides a bullet collecting system for preventing occurrence of lead fume in the indoor shooting range, in which the beaten zone of the indoor shooting range is newly improved from an existing system of using an iron plate to a system of using powder filling materials, thereby preventing the leakage of lead fume, and contributing to an early normalization of the shooting range and a creative national defense.

Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.

Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.

Abstract: Provided is a composition for producing astringin among metabolites of polydatin, wherein the astringin may be mass-produced by oxidizing the polydatin using a CYP102A1 chimera and mutants thereof as a catalyst, the CYP102A1 chimera being produced by fusing a reductase domain of a wild-type CYP102A1 which is a bacterial cytochrome P450 enzyme, with a heme domain of a CYP102A1 mutant.

Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.