Patents by Inventor Hee Joung

Hee Joung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12345510
    Abstract: An indoor live ammunition shooting range facility system includes a ventilation facility installed in an indoor live ammunition shooting range, and configured to ventilate air of the indoor live ammunition shooting range; a targeting device facility installed in the indoor live ammunition shooting range, and configured to provide a shooting target; a bulletproof facility installed to protect components exposed to an inside of the indoor live ammunition shooting range among components configuring the ventilation facility and the target device facility and to protect a wall surface of the indoor live ammunition shooting range; a bullet head recovery facility installed on a side opposite to a shooting position, and configured to recover a bullet head; and a control facility installed in the indoor live ammunition shooting range, and configured to control the ventilation facility, the target device facility and the bullet head recovery facility.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 1, 2025
    Assignee: EA-GAIA INC.
    Inventors: Hee Joung Kim, Min A Gang, Sun Gu Kim, Sun Jae Kim
  • Publication number: 20250149106
    Abstract: A memory system comprising a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches coupled to the bit lines, and configured to program input data stored in the latches into memory cells of a selected word line during a program operation, and output, as information data, at least one or more data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation, and a controller configured to repair the input data by performing a set logic operation on the information data from the memory device, and apply the set logic operation whose type is different according to an execution moment of the program suspend operation.
    Type: Application
    Filed: September 4, 2024
    Publication date: May 8, 2025
    Inventors: Hee Joung PARK, Chang Han SON, Hyun Seob SHIN, Myung Su KIM, Sung Hun KIM, Kang Woo PARK, Ming ZHANG, Yogesh WAKCHAURE, Curtis GITTENS, Zion KWOK, Bing XIAO, Hui-chun WU
  • Publication number: 20250135584
    Abstract: A groove forming apparatus includes a laser light source configured to emit a laser beam, a multi-beam generator configured to split the laser beam into a plurality of sub-laser beams, a focusing lens unit configured to focus the plurality of sub-laser beams on a processing object, a first telecentric lens provided between the multi-beam generator and the focusing lens unit, and a second telecentric lens provided between the first telecentric lens and the focusing lens unit.
    Type: Application
    Filed: September 14, 2022
    Publication date: May 1, 2025
    Applicant: EO TECHNICS CO.,LTD.
    Inventors: Woong Hee JOUNG, Jung Rae PARK, Byung Oh KIM, Dong Jun LEE, Jun Young LEE, Geun Haeng LEE, Chan Hee KANG
  • Publication number: 20250038116
    Abstract: A printed circuit board may include: a first substrate unit including a plurality of build-up insulating layers and a plurality of build-up wiring layers respectively disposed on or in the plurality of build-up insulating layers; and a second substrate unit including a glass layer, first and second wiring layers disposed above and below the glass layer, respectively, an insulating layer disposed above the glass layer, and a third wiring layer disposed above the insulating layer, wherein the second substrate unit is stacked on the first substrate unit or embedded in the first substrate unit, wherein an average pitch of circuits of each of the first to third wiring layers is lower than an average pitch of circuits of each of the plurality of build-up wiring layers.
    Type: Application
    Filed: February 20, 2024
    Publication date: January 30, 2025
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Da Hee JOUNG, Bong Wan KOO, Jee Hoon KIM
  • Patent number: 11880582
    Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Publication number: 20230003493
    Abstract: An indoor live ammunition shooting range facility system includes a ventilation facility installed in an indoor live ammunition shooting range, and configured to ventilate air of the indoor live ammunition shooting range; a targeting device facility installed in the indoor live ammunition shooting range, and configured to provide a shooting target; a bulletproof facility installed to protect components exposed to an inside of the indoor live ammunition shooting range among components configuring the ventilation facility and the target device facility and to protect a wall surface of the indoor live ammunition shooting range; a bullet head recovery facility installed on a side opposite to a shooting position, and configured to recover a bullet head; and a control facility installed in the indoor live ammunition shooting range, and configured to control the ventilation facility, the target device facility and the bullet head recovery facility.
    Type: Application
    Filed: December 17, 2020
    Publication date: January 5, 2023
    Applicant: EA-GAIA INC.
    Inventors: Hee Joung KIM, Min A GANG, Sun Gu KIM, Sun Jae KIM
  • Patent number: 11502391
    Abstract: An electronic device may have an antenna that conveys radio-frequency signals at frequencies greater than 10 GHz. The antenna may be embedded in a substrate. The substrate may have routing layers, first antenna layers on the routing layers, second antenna layers on the first antenna layers, and a third antenna layers on the second antenna layers. The antenna may include first traces on the first antenna layers, second traces on the second antenna layers, and third traces on the third antenna layers. The first antenna layers may have a first bulk dielectric permittivity. The second layers may have a second bulk dielectric permittivity. The third layers may have a third bulk dielectric permittivity. At least one of the first, second, and third bulk dielectric permittivities may be different from the others. This may differentially load the antenna across the antenna layers, thereby broadening the bandwidth of the antenna.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 15, 2022
    Assignee: Apple Inc.
    Inventors: Siwen Yong, Jiangfeng Wu, Yi Jiang, Simon G. Begashaw, Harish Rajagopalan, Hee-Joung Joun, Thomas W. Yang, Mattia Pascolini
  • Publication number: 20220094036
    Abstract: An electronic device may have an antenna that conveys radio-frequency signals at frequencies greater than 10 GHz. The antenna may be embedded in a substrate. The substrate may have routing layers, first antenna layers on the routing layers, second antenna layers on the first antenna layers, and a third antenna layers on the second antenna layers. The antenna may include first traces on the first antenna layers, second traces on the second antenna layers, and third traces on the third antenna layers. The first antenna layers may have a first bulk dielectric permittivity. The second layers may have a second bulk dielectric permittivity. The third layers may have a third bulk dielectric permittivity. At least one of the first, second, and third bulk dielectric permittivities may be different from the others. This may differentially load the antenna across the antenna layers, thereby broadening the bandwidth of the antenna.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Siwen Yong, Jiangfeng Wu, Yi Jiang, Simon G. Begashaw, Harish Rajagopalan, Hee-Joung Joun, Thomas W. Yang, Mattia Pascolini
  • Patent number: 11114163
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Publication number: 20210165603
    Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10950306
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Publication number: 20200294597
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Publication number: 20200294596
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Patent number: 10706929
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
  • Publication number: 20200211650
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Application
    Filed: July 12, 2019
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10304544
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin, Dong Hyuk Chae
  • Publication number: 20190043584
    Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.
    Type: Application
    Filed: March 23, 2018
    Publication date: February 7, 2019
    Applicant: SK hynix Inc.
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
  • Patent number: 10190855
    Abstract: The present invention provides a bullet collecting box which is installed with a plurality of rubber plates in the bullet collecting box having a rectangular parallelepiped shape and filled with rubber powder filling materials having a particle size of 0.1 to 3 mm therein, thereby collecting the bullets fired in the indoor shooting range without damage, and a bullet collecting system which can be used by installing the bullet collecting box in the indoor shooting range. Also, the present invention provides a bullet collecting system for preventing occurrence of lead fume in the indoor shooting range, in which the beaten zone of the indoor shooting range is newly improved from an existing system of using an iron plate to a system of using powder filling materials, thereby preventing the leakage of lead fume, and contributing to an early normalization of the shooting range and a creative national defense.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 29, 2019
    Inventors: Hee Joung Kim, Min A Kang, Sun Jae Kim, Sun Gu Kim
  • Publication number: 20180322929
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Application
    Filed: December 8, 2017
    Publication date: November 8, 2018
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN, Dong Hyuk CHAE
  • Patent number: 9965388
    Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 8, 2018
    Assignee: SK Hynix Inc.
    Inventors: Ki Chang Chun, Hee Joung Park, Tae Seung Shin, Sung Lae Oh