Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the semiconductor substrate. Next, the mask pattern is removed to expose the first gate insulating pattern and a second gate insulating layer is formed on the entire surface thereof. The mask pattern is preferably formed of an anti-reflecting pattern and a photoresist pattern that are sequentially stacked. The anti-reflecting pattern is preferably formed of a material layer without etching selectivity with respect to the photoresist pattern. For this, the anti-reflecting pattern is preferably formed of organic materials including hydrocarbonic compounds. In addition, removing a mask pattern is performed with an etch recipe having an etch selectivity with respect to the first gate insulating pattern.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the semiconductor substrate. Next, the mask pattern is removed to expose the first gate insulating pattern and a second gate insulating layer is formed on the entire surface thereof. The mask pattern is preferably formed of an anti-reflecting pattern and a photoresist pattern that are sequentially stacked. The anti-reflecting pattern is preferably formed of a material layer without etching selectivity with respect to the photoresist pattern. For this, the anti-reflecting pattern is preferably formed of organic materials including hydrocarbonic compounds. In addition, removing a mask pattern is performed with an etch recipe having an etch selectivity with respect to the first gate insulating pattern.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.