Patents by Inventor Hee-Jun BYEON
Hee-Jun BYEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9823531Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.Type: GrantFiled: May 14, 2014Date of Patent: November 21, 2017Assignee: Samsung Display Co., Ltd.Inventors: Tae-Young Choi, Bo Sung Kim, Jae Woo Park, Hee Jun Byeon, Young-Wook Lee, Moon-Keun Choi
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Patent number: 9647136Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.Type: GrantFiled: June 18, 2015Date of Patent: May 9, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
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Patent number: 9524992Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: GrantFiled: October 5, 2015Date of Patent: December 20, 2016Assignee: Samsung Display Co., Ltd.Inventors: Hye Young Ryu, Hee Jun Byeon, Woo Geun Lee, Kap Soo Yoon, Yoon Ho Kim, Chun Won Byun
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Patent number: 9455276Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.Type: GrantFiled: August 11, 2014Date of Patent: September 27, 2016Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hee Jun Byeon, Seung Sok Son, Bo Sung Kim, Yeon Taek Jeong
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Publication number: 20160027805Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Hye Young RYU, Hee Jun BYEON, Woo Geun LEE, Kap Soo YOON, Yoon Ho KIM, Chun Won BYUN
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Publication number: 20150287836Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
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Patent number: 9153600Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: GrantFiled: September 14, 2012Date of Patent: October 6, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hye Young Ryu, Hee Jun Byeon, Woo Geun Lee, Kap Soo Yoon, Yoon Ho Kim, Chun Won Byun
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Patent number: 9117917Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.Type: GrantFiled: October 12, 2012Date of Patent: August 25, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
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Patent number: 9059112Abstract: A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer.Type: GrantFiled: April 15, 2014Date of Patent: June 16, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yeon Taek Jeong, Hee Jun Byeon
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Publication number: 20150162349Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.Type: ApplicationFiled: August 11, 2014Publication date: June 11, 2015Inventors: Hee Jun BYEON, Seung Sok SON, Bo Sung KIM, Yeon Taek JEONG
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Publication number: 20150162251Abstract: A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer.Type: ApplicationFiled: April 15, 2014Publication date: June 11, 2015Applicant: Samsung Display Co., Ltd.Inventors: Yeon Taek JEONG, Hee Jun BYEON
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Patent number: 8994023Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.Type: GrantFiled: May 24, 2011Date of Patent: March 31, 2015Assignee: Samsung Display Co., Ltd.Inventors: Hye-Young Ryu, Woo-Geun Lee, Young-Joo Choi, Kyoung-Jae Chung, Jin-Won Lee, Seung-Ha Choi, Hee-Jun Byeon, Pil-Sang Yun
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Patent number: 8969131Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.Type: GrantFiled: December 2, 2013Date of Patent: March 3, 2015Assignee: Samsung Display Co., Ltd.Inventors: Hye-Young Ryu, Jin-Won Lee, Woo-Geun Lee, Hee-Jun Byeon, Xun Zhu
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Publication number: 20150049276Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.Type: ApplicationFiled: May 14, 2014Publication date: February 19, 2015Applicant: Samsung Display Co., Ltd.Inventors: Tae-Young CHOI, Bo Sung KIM, Jae Woo PARK, Hee Jun BYEON, Young-Wook LEE, Moon-Keun CHOI
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Patent number: 8866137Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.Type: GrantFiled: February 3, 2012Date of Patent: October 21, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jin-Won Lee, Woo Geun Lee, Kap Soo Yoon, Ki-Won Kim, Hyun-Jung Lee, Hee-Jun Byeon, Ji-Soo Oh
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Publication number: 20140093998Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.Type: ApplicationFiled: December 2, 2013Publication date: April 3, 2014Applicant: Samsung Display Co., Ltd.Inventors: Hye-Young Ryu, Jin-Won Lee, Woo-Geun Lee, Hee-Jun Byeon, Xun Zhu
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Patent number: 8598583Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.Type: GrantFiled: April 22, 2011Date of Patent: December 3, 2013Assignee: Samsung Display Co., Ltd.Inventors: Hye-Young Ryu, Jin-Won Lee, Woo-Geun Lee, Hee-Jun Byeon, Xun Zhu
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Publication number: 20130214299Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.Type: ApplicationFiled: September 14, 2012Publication date: August 22, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Hye Young RYU, Hee Jun BYEON, Woo Geun LEE, Kap Soo YOON, Yoon Ho KIM, Chun Won BYUN
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Publication number: 20130099240Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.Type: ApplicationFiled: October 12, 2012Publication date: April 25, 2013Applicant: Samsung Display Co., Ltd.Inventors: Hyun-Jung LEE, Sung-Haeng CHO, Woo-Geun LEE, Jang-Hoon HA, Hee-Jun BYEON, Ji-Yun HONG, Ji-Soo OH
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Publication number: 20120217493Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.Type: ApplicationFiled: February 3, 2012Publication date: August 30, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Won LEE, Woo Geun LEE, Kap Soo YOON, Ki-Won KIM, Hyun-Jung LEE, Hee-Jun BYEON, Ji-Soo OH