Abstract: In one example, an electronic device includes a first substrate, an electronic component coupled to a side of the first substrate, and a vertical interconnect structure coupled to the side of the first substrate. The vertical interconnect structure includes a first interconnect structure coupled to the side of the first substrate, and an intermediate substrate having a first side coupled to the first interconnect structure. The intermediate substrate comprises inner sidewalls defining a cavity with the electronic component extending through the cavity. A second interconnect structure can be coupled to a second side of the intermediate substrate opposite the first side of the intermediate substrate. An encapsulant can be disposed over the first substrate and the intermediate substrate, around the electronic component, around the first interconnect structure, around the second interconnect structure, and around the intermediate substrate. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device comprises a first substrate comprising a first conductive structure, a first electronic component over a first side of the first substrate and coupled to the first conductive structure, a second substrate over the first substrate and over the first electronic component, wherein the second substrate comprises a second conductive structure, an internal interconnect between the first substrate and the second substrate and coupled to the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering a lateral side of the first electronic component and a lateral side of the internal interconnect. A first one of the first substrate and the second substrate comprises a redistribution layer (R D L) substrate, and a second one of the first substrate and the second substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

Abstract: An example method of manufacturing an electronic device can include providing a device wafer including an active region comprising a front-end-of-line (FEOL) region opposite a back-end-of-line (BEOL) region. The FEOL region can include buried power rails, and the BEOL region can include a dielectric structure having a side exposed from the BEOL region. A support substrate having a substrate dielectric can be coupled to the dielectric structure. A bond interface is disposed between the substrate dielectric and the dielectric structure. A passivation structure can be provided over the FEOL region. Conductive vias can be provided through the passivation structure. The conductive vias can include a conductor coupled to the buried power rails. A substrate can be coupled to the passivation structure. The substrate can include a power network electrically coupled to the conductive vias.

Abstract: In one example, an electronic device can include an active region comprising a channel region. A first isolation region may be disposed at a lateral side of the channel region. A source region may be located in a footprint of the channel region and disposed between the channel region and the first isolation region. A device passivation can cover a side of the channel region opposite the source region and disposed on a lateral side of the first isolation region. A substrate passivation can be coupled to the device passivation. A bond interface can be disposed between the device passivation and the substrate passivation. A substrate can be coupled to the substrate passivation. Other examples and related methods are also disclosed herein.

Abstract: A method of manufacturing an electronic device includes providing vertical interconnects over a first carrier and bonding an inorganic layer of a routing component to an inorganic layer of the first carrier. The method also includes encapsulating the vertical interconnects and the routing component in a lower encapsulant and providing an upper substrate such that a conductive structure of the upper substrate is coupled to the vertical interconnects and to an upper side of the routing component. The method further includes coupling a first electronic component and a second electronic component to the upper substrate and providing a second carrier over the first electronic component and the second electronic component. The method may also include removing the first carrier and providing a lower substrate such that a conductive structure of the lower substrate is coupled to the vertical interconnects. Other methods and related electronic devices are also disclosed.

Abstract: In one example, a redistribution structure is provided and comprises a substrate interconnect. A portion of a first capping layer is removed to expose a side of the substrate interconnect. The side of the substrate interconnect is recessed by a dishing height from a side of the first capping layer. An electronic component is provided over the first capping layer. The electronic component comprises a second capping layer and a component interconnect. The second capping layer is bonded with the first capping layer. Heat is applied to bond the substrate interconnect to the component interconnect. Other examples and related devices and methods are also disclosed herein.

Abstract: In one example, an electronic device comprises a first and second substrates comprising first and second dielectric structures and first and second conductive structures, a first electronic component over the first substrate, the second substrate being over the first substrate and the first electronic component, a first interconnect structure between the first substrate and the second substrate and coupled with the first conductive structure and the second conductive structure, a first encapsulant between the first substrate and the second substrate and covering a lateral side of the first interconnect structure and a lateral side of the first electronic component, a second interconnect structure over the second substrate and coupled with the second conductive structure, a second encapsulant over the second substrate and covering a lateral side of the second interconnect structure, and a photonic integrated circuit over the second encapsulant and coupled with the second interconnect structure.