Abstract: A display device include a substrate, a pixel electrode disposed on the substrate, a partition layer disposed on the substrate and defining an opening exposing at least a part of the pixel electrode, a light-emitting layer disposed on the pixel electrode within the opening of the partition layer, a common electrode disposed on the light-emitting layer within the opening of the partition layer, a capping layer disposed on the common electrode and the partition layer, and surrounding a side surface of the opening of the partition layer, and a color conversion pattern disposed on the capping layer within the opening of the partition layer.

Abstract: A filter cartridge includes a housing, a filter member disposed within the housing, and an endcap disposed within the housing between the filter member and the housing. The housing includes a first end with an inlet, a second end opposite to the first end, and an outlet. The filter member includes a first axial end that faces the first end of the housing and a second axial end that faces the second end of the housing. The endcap including an outer side that faces the first end of the housing and fins that project from the outer side of the endcap. The fins configured to redirect the fluid flowing into the filter cartridge through the inlet in the housing.

Abstract: A display device includes a first substrate including a first contact hole, fan-out lines in a first metal layer, a second substrate on the first metal layer and including a second contact hole, connection lines in a second metal layer and into the second contact hole connected to the fan-out lines, a thin film transistor in an active layer and a third metal layer on the second metal layer, and a flexible film on a surface of the first substrate and into the first contact hole connected to the fan-out lines. An etching angle of the first contact hole between a top surface of the first substrate and an inner surface of the first contact hole is less than an etching angle of the second contact hole between top surfaces of the fan-out lines and an inner surface of the second contact hole.

Abstract: A method for manufacturing a display device according to an embodiment includes: forming a display panel including a first substrate, a second substrate facing the first substrate, an emission layer disposed between the first substrate and the second substrate, a pad portion disposed on the first substrate, and a thin film encapsulation layer disposed on the pad portion; removing the thin film encapsulation layer disposed on the pad portion by using a plasma processing device; and attaching a flexible circuit board on which an integrated circuit chip is mounted to the pad portion exposed by removing the thin film encapsulation layer.

Abstract: A filter that is self-locking to a filter manifold includes a flange having a major axis and a minor axis in plan view, and that is longer along the major axis than the minor axis. The filter further includes a stopper on the major axis, that can contact a filter manifold when the filter is inserted into the manifold and rotated. The filter can be used with a filter manifold having a slot with an opening having a width greater than the length of the minor axis and smaller than the length along the major axis of the flange, and past the opening, has sufficient width to accommodate the length of the major axis. This arrangement allows the flange to be inserted into the slot in an insertion orientation, but does not permit the flange to pass through the opening of the slot when it is in a locking position.

Abstract: Non-disperse, periodic microplasmas are generated in a volume lacking interfering structures, such as electrodes, to enable photonic interaction between incident electromagnetic energy and the non-disperse, periodic microplasmas. Preferred embodiments leverage 1D, 2D, 3D and super 3D non-disperse, periodic microplasmas. In preferred embodiments, the non-disperse, periodic microplasmas are elongate columnar microplasmas. In other embodiments, the non-disperse, periodic microplasmas are discrete isolated microplasmas. The photonic properties can change by selectively activating groups of the periodic microplasmas.

Abstract: Non-disperse, periodic microplasmas are generated in a volume lacking interfering structures, such as electrodes, to enable photonic interaction between incident electromagnetic energy and the non-disperse, periodic microplasmas. Preferred embodiments leverage 1D, 2D, 3D and super 3D non-disperse, periodic microplasmas. In preferred embodiments, the non-disperse, periodic microplasmas are elongate columnar microplasmas. In other embodiments, the non-disperse, periodic microplasmas are discrete isolated microplasmas. The photonic properties can change by selectively activating groups of the periodic microplasmas.

Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.

Abstract: A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.

Abstract: According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate.