Abstract: A polymeric light-emitting diode (PLED) and methods of making same. In one embodiment, the PLED comprises a substrate, a layer of a first conductive material formed on a surface of the substrate, a layer of a conductive polymeric material deposited on the layer of the first conductive material, a layer of a luminescent polymeric material deposited on the layer of the conductive polymeric material, and a layer of a second conductive material formed on the layer of the luminescent polymeric material, wherein at least one of the layer of the conductive polymeric material and the layer of the luminescent polymeric material is deposited by the laser vapor deposition (LVD).

Abstract: The invention relates to the deposition or transfer of material using a laser induced forward transfer process. More specifically, the invention relates to the transfer of material using a laser induced forward transfer process wherein the transfer process is facilitated or enabled by nanomaterials. Nanomaterials in the form of nanoparticles or nanofilms may be employed, optionally including a surface coating or self-assembled monolayer surface coating, making use of properties of the nanomaterials that allow the laser induced forward transfer process to be practiced at irradiation energies and temperatures lower than commonly used. The technique may be well suited for depositing organic layers.

Abstract: A method for manufacturing a semiconductor device including the steps of forming a photoresist pattern on a metal layer and forming a wiring by etching a metal composed of aluminum or aluminum alloy with plasma including chlorine and eliminating said photoresist pattern while simultaneously eliminating residual chlorine on the wiring by adding alkyl ketone or alkyl ether in an oxygen plasma ash chamber. The present invention can provide a method for manufacturing a semiconductor device, which can eliminate residual chlorine and a photoresist pattern by adding alkyl ketone or alkyl ether so that wiring corrosion may be prevented.

Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.

Abstract: Present invention relates to the fabrication method of the bipolar transistor.With this method the emitter of high-concentrated n-type is contacted closely to the extrinsic base of high-concentrated p-type.This structure is obtained by making the emitter of the bipolar transistor be self- aligned by the side wall under-cut of the nitride layer using double layers of the low temperature oxide and the nitride layer.

Abstract: An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall.

Abstract: A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.