Patents by Inventor Hee Kon Lee
Hee Kon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8830689Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.Type: GrantFiled: September 15, 2011Date of Patent: September 9, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Gu Kim, Mi Jin Park, Young Ho Kim, Seung Wook Park, Hee Kon Lee, Young Do Kweon
-
Patent number: 8704350Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.Type: GrantFiled: July 13, 2009Date of Patent: April 22, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Jing Li Yuan, Jong Yun Lee
-
Patent number: 8658467Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.Type: GrantFiled: February 9, 2011Date of Patent: February 25, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Yuan Jing Li, Jong Yun Lee
-
Publication number: 20120067636Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.Type: ApplicationFiled: September 15, 2011Publication date: March 22, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu KIM, Mi Jin KIM, Young Ho KIM, Seung Wook PARK, Hee Kon LEE, Young Do KWEON
-
Publication number: 20110201156Abstract: A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.Type: ApplicationFiled: April 22, 2011Publication date: August 18, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
-
Publication number: 20110198749Abstract: Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection.Type: ApplicationFiled: February 15, 2011Publication date: August 18, 2011Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Hee Kon Lee, Ju Pyo Hong, Eun Kyung Jeon, Seung Wook Park, Young Do Kweon, Jin Gu Kim
-
Publication number: 20110156241Abstract: Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips.Type: ApplicationFiled: February 24, 2010Publication date: June 30, 2011Inventors: Ju Pyo HONG, Young Do Kweon, Jin Gu Kim, Seung Wook Park, Hee Kon Lee
-
Publication number: 20110129960Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.Type: ApplicationFiled: February 9, 2011Publication date: June 2, 2011Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Yuan Jing Li, Jong Yun Lee
-
Patent number: 7947530Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.Type: GrantFiled: May 5, 2009Date of Patent: May 24, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
-
Publication number: 20100159646Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.Type: ApplicationFiled: May 5, 2009Publication date: June 24, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
-
Publication number: 20100117218Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.Type: ApplicationFiled: July 13, 2009Publication date: May 13, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Jing Li Yuan, Jong Yun Lee