Abstract: The present invention relates to an organic anti-reflective composition and a patterning method using the same, more particularly to an organic anti-reflective composition comprising a crosslinking agent, a light absorbing agent, a thermal acid generator, an organic solvent and an adhesivity enhancer, and a patterning method using the same. The organic anti-reflective composition of the present invention can solve the standing wave effect due to change in optical properties and resist thickness of the bottom film on the wafer, prevent change of critical dimension (CD) due to scattered reflection, and prevent pattern collapse of photosensitizer on top of the organic anti-reflective film, and thus can form stable 64 M, 256 M, 512 M, 1 G, 4 G and 16 G DRAM ultrafine pattern and of improving product yield.

Abstract: A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact.

Abstract: A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact.