Patents by Inventor Hee Min SHIN

Hee Min SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404863
    Abstract: A method for fabricating a semiconductor device may include forming a first substrate including a first surface and a second surface, which may be opposite each other, forming a first semiconductor element on the first surface, adhering the first substrate onto a second substrate so that an upper surface of the second substrate faces the first surface of the first substrate, removing an edge region of the first substrate, forming a passivation layer surrounding first sides of the first substrate, and forming a second semiconductor element on the second surface of the first substrate. The passivation layer may not be formed on the second surface of the first substrate.
    Type: Application
    Filed: January 9, 2024
    Publication date: December 5, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kwang Yong YU, Woo Jeong SHIN, Il Hwan KIM, Chang Min PARK, Hee Sun JUN
  • Publication number: 20240339702
    Abstract: The present disclosure is directed to a film for a cell pouch and a manufacturing method thereof. A cell pouch film and a manufacturing method thereof according to an example embodiment of the present disclosure has good mechanical strength, low deviation in mechanical strength due to low stress on the film, and good formability.
    Type: Application
    Filed: April 7, 2024
    Publication date: October 10, 2024
    Applicant: Youlchon Chemical Co., Ltd.
    Inventors: Nok Jung Song, Hee Sik Han, Huihun Kim, Ji Min Lee, Han Chul Park, Doohee Lee, Geon Ryong Kim, Sung Chul Shin, Moonkyu Song
  • Publication number: 20240298654
    Abstract: The present invention relates to a method for preparing dough for frozen pizza, dough for frozen pizza prepared by the preparation method, and frozen pizza comprising the same.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 12, 2024
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jae Kyoung CHOI, Hye Won SHIN, Eun Yi KIM, Sang Geun KIM, Young Min HA, Hee Soo PARK, Min Hyuk KIM, Ki Moon KANG
  • Patent number: 9842809
    Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Ill Moon, Myeong Seob Kim, Hee Min Shin
  • Patent number: 9659909
    Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: Hee Min Shin, Mi Young Kim
  • Publication number: 20170084579
    Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 23, 2017
    Inventors: Hee Min SHIN, Mi Young KIM
  • Publication number: 20170047293
    Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.
    Type: Application
    Filed: January 6, 2016
    Publication date: February 16, 2017
    Inventors: Ki Ill MOON, Myeong Seob KIM, Hee Min SHIN
  • Patent number: 9305912
    Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hee Min Shin, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Kyu Won Lee
  • Publication number: 20150270252
    Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.
    Type: Application
    Filed: June 9, 2015
    Publication date: September 24, 2015
    Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
  • Patent number: 9093441
    Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ji Eun Kim, Cheol Ho Joh, Hee Min Shin, Kyu Won Lee, Chong Ho Cho
  • Patent number: 9082634
    Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hee-Min Shin, Cheol-Ho Joh, Eun-Hye Do, Ji-Eun Kim, Kyu-Won Lee
  • Patent number: 8951810
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: SK hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
  • Publication number: 20140175638
    Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 26, 2014
    Applicant: SK HYNIX INC.
    Inventors: Ji Eun KIM, Cheol Ho JOH, Hee Min SHIN, Kyu Won LEE, Chong Ho CHO
  • Publication number: 20140057369
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Application
    Filed: December 18, 2012
    Publication date: February 27, 2014
    Applicant: SK hynix Inc.
    Inventors: Kyu Won LEE, Cheol-Ho JOH, Ji Eun KIM, Hee-Min SHIN, Chong Ho CHO
  • Patent number: 8564141
    Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: October 22, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Hee Min Shin
  • Publication number: 20130256887
    Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Applicant: SK hynix Inc.
    Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
  • Patent number: 8476751
    Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: July 2, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
  • Publication number: 20120018879
    Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.
    Type: Application
    Filed: December 29, 2010
    Publication date: January 26, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hee-Min SHIN, Cheol-Ho JOH, Eun-Hye DO, Ji-Eun KIM, Kyu-Won LEE
  • Publication number: 20110272820
    Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 10, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
  • Publication number: 20110272798
    Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.
    Type: Application
    Filed: March 2, 2011
    Publication date: November 10, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyu Won LEE, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Hee Min SHIN