Patents by Inventor Hee Min SHIN
Hee Min SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962001Abstract: Disclosed is a positive electrode material for a lithium secondary battery. The positive electrode material includes a positive electrode active material formed of Li—[Mn—Ti]-M-O-based material including a transition metal (M) to enable reversible intercalation and deintercalation of lithium and molybdenum oxide. The positive electrode active material is coated with the molybdenum oxide to form a coating layer on a surface thereof.Type: GrantFiled: October 6, 2021Date of Patent: April 16, 2024Assignees: Hyundai Motor Company, Kia Corporation, Industry Academy Cooperation Foundation of Sejong UniversityInventors: Seung Min Oh, Jun Ki Rhee, Yoon Sung Lee, Ji Eun Lee, Sung Ho Ban, Ko Eun Kim, Woo Young Jin, Sang Mok Park, Sang Hun Lee, Seung Taek Myung, Hee Jae Kim, Min Young Shin
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Publication number: 20240082345Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.Type: ApplicationFiled: August 25, 2021Publication date: March 14, 2024Applicant: HLB SCIENCE INC.Inventors: Yeong Min PARK, Wahn Soo CHOI, Seung-Hyun LEE, In Duk JUNG, Yong Joo KIM, Seung Jun LEE, Sung Min KIM, Mi Suk LEE, Hee Jo PARK, Seung Pyo CHOI, Minho MOON, Soo Jung SHIN, Sujin KIM, Yong Ho PARK, Jae-Yong PARK, Kun Ho LEE
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Patent number: 9842809Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.Type: GrantFiled: January 6, 2016Date of Patent: December 12, 2017Assignee: SK hynix Inc.Inventors: Ki Ill Moon, Myeong Seob Kim, Hee Min Shin
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Patent number: 9659909Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.Type: GrantFiled: February 2, 2016Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Hee Min Shin, Mi Young Kim
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Publication number: 20170084579Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.Type: ApplicationFiled: February 2, 2016Publication date: March 23, 2017Inventors: Hee Min SHIN, Mi Young KIM
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Publication number: 20170047293Abstract: A semiconductor package may include a semiconductor device mounted on a package substrate, a conductive roof located over the semiconductor device, a plurality of conductive walls disposed on the package substrate and arrayed in a closed loop line surrounding the semiconductor device. Conductive pillars may be disposed in regions between the conductive walls on the package substrate and bonded to the conductive roof. The semiconductor package may include a first dielectric layer filling a space between the package substrate and the conductive roof.Type: ApplicationFiled: January 6, 2016Publication date: February 16, 2017Inventors: Ki Ill MOON, Myeong Seob KIM, Hee Min SHIN
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Patent number: 9305912Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: June 9, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Hee Min Shin, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Kyu Won Lee
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Publication number: 20150270252Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: June 9, 2015Publication date: September 24, 2015Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
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Patent number: 9093441Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.Type: GrantFiled: March 18, 2013Date of Patent: July 28, 2015Assignee: SK Hynix Inc.Inventors: Ji Eun Kim, Cheol Ho Joh, Hee Min Shin, Kyu Won Lee, Chong Ho Cho
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Patent number: 9082634Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: December 29, 2010Date of Patent: July 14, 2015Assignee: SK Hynix Inc.Inventors: Hee-Min Shin, Cheol-Ho Joh, Eun-Hye Do, Ji-Eun Kim, Kyu-Won Lee
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Patent number: 8951810Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.Type: GrantFiled: December 18, 2012Date of Patent: February 10, 2015Assignee: SK hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
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Publication number: 20140175638Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.Type: ApplicationFiled: March 18, 2013Publication date: June 26, 2014Applicant: SK HYNIX INC.Inventors: Ji Eun KIM, Cheol Ho JOH, Hee Min SHIN, Kyu Won LEE, Chong Ho CHO
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Publication number: 20140057369Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: Kyu Won LEE, Cheol-Ho JOH, Ji Eun KIM, Hee-Min SHIN, Chong Ho CHO
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Patent number: 8564141Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: GrantFiled: March 2, 2011Date of Patent: October 22, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20130256887Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Applicant: SK hynix Inc.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
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Patent number: 8476751Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: GrantFiled: April 28, 2011Date of Patent: July 2, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20120018879Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: December 29, 2010Publication date: January 26, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hee-Min SHIN, Cheol-Ho JOH, Eun-Hye DO, Ji-Eun KIM, Kyu-Won LEE
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Publication number: 20110272820Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: April 28, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
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Publication number: 20110272798Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: ApplicationFiled: March 2, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Hee Min SHIN
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WAFER MOUNT TAPE, WAFER PROCESSING APPARATUS AND METHOD OF USING THE SAME FOR USE IN THINNING WAFERS
Publication number: 20110189928Abstract: A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive is member is disposed at the first region. The second adhesive member is disposed at the third region.Type: ApplicationFiled: March 17, 2011Publication date: August 4, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE