Patents by Inventor Hee-ok KIM

Hee-ok KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128443
    Abstract: A silicon-carbon containing electrode material includes a porous carbon structure including pores, and a silicon-containing coating formed on the porous carbon structure. A volume ratio of mesopores is 70% or more based on a total pore volume of the porous carbon structure. A weight ratio of silicon is 30 wt % or more based on a total weight of the electrode material. A high-capacity secondary battery is effectively implemented by using silicon-carbon containing electrode material.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 18, 2024
    Inventors: Hee Soo KIM, Yeon Ho KIM, Young Kwang KIM, Young Eun CHEON, Gwi Ok PARK, Seok Keun YOO
  • Patent number: 11832486
    Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: November 28, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong-Heon Yang, Seung Youl Kang, Yong Hae Kim, Hee-ok Kim, Jeho Na, Jaehyun Moon, Chan Woo Park, Himchan Oh, Seong-Mok Cho, Sung Haeng Cho, Ji Hun Choi, Jae-Eun Pi, Chi-Sun Hwang
  • Publication number: 20230091070
    Abstract: Provided are stretchable electronics and a method for manufacturing the same. The stretchable electronics may include a substrate, a plurality of electronic elements disposed to be spaced apart from each other on the substrate, and a wire structure disposed on the substrate to connect the plurality of electronic elements to each other. The wire structure may include an insulator extending from one of the electronic elements to the other of the adjacent electronic elements and a metal wire configured to cover a top surface and side surfaces of the insulator. The insulator may include at least one bent part in a plan view.
    Type: Application
    Filed: August 16, 2022
    Publication date: March 23, 2023
    Inventors: Ji Hun CHOI, Chan Woo PARK, Ji-Young OH, Seung Youl KANG, Yong Hae KIM, Hee-ok KIM, Jeho NA, Jaehyun MOON, Jong-Heon YANG, Himchan OH, Seong-Mok CHO, Sung Haeng CHO, Jae-Eun PI, Chi-Sun HWANG
  • Publication number: 20230083225
    Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 16, 2023
    Inventors: Jong-Heon YANG, Seung Youl KANG, Yong Hae KIM, Hee-ok KIM, Jeho NA, Jaehyun MOON, Chan Woo PARK, Himchan OH, Seong-Mok CHO, Sung Haeng CHO, Ji Hun CHOI, Jae-Eun PI, Chi-Sun HWANG
  • Publication number: 20220179359
    Abstract: Disclosed is an apparatus of analyzing a depth of a holographic image according to the present disclosure, which includes an acquisition unit that acquires a hologram, a restoration unit that restores a three-dimensional holographic image by irradiating the hologram with a light source, an image sensing unit that senses a depth information image of the restored holographic image, and an analysis display unit that analyzes a depth quality of the holographic image, based on the sensed depth information image, and the image sensing unit uses a lensless type of photosensor.
    Type: Application
    Filed: November 10, 2021
    Publication date: June 9, 2022
    Applicants: Electronics and Telecommunications Research Institute, MVTECH
    Inventors: Jae-Eun PI, Yong Hae KIM, Jong-Heon YANG, Chul Woong JOO, Chi-Sun HWANG, HA KYUN LEE, Seung Youl KANG, Gi Heon KIM, Joo Yeon KIM, Hee-ok KIM, Jeho NA, Jaehyun MOON, Won Jae LEE, Seong-Mok CHO, Ji Hun CHOI
  • Publication number: 20130119468
    Abstract: A thin-film transistor may include a drain electrode, a source electrode, an active layer, a gate electrode, and a gate insulating layer. In a vertical sectional view, the gate insulating layer may be disposed between the active layer and the gate electrode to include a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked. According to a method of fabricating the thin-film transistor, the gate insulating layer may be formed between the steps of forming the active layer and the second electrode layer or between the steps of forming the first electrode layer and the second electrode layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: May 16, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Chul LIM, Jiyoung OH, Seung Youl KANG, Hee-ok KIM, Kyoung Ik CHO, Seongdeok AHN