Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.

Abstract: Disclosed are an apparatus for distributing power of an electric vehicle and a method thereof capable of optimally improving the energy consumption efficiency of the electric vehicle by predicting a vehicle speed for a predetermined time using a learned vehicle speed prediction model, determining wheel power based on the vehicle speed, and distributing the wheel power to a front wheel drive motor and a rear wheel drive motor. The apparatus includes a storage that stores a vehicle speed prediction model in which learning is completed, and a controller that predicts a vehicle speed for a preset time using the vehicle speed prediction model, determines wheel power based on the vehicle speed, and distributes the wheel power to a front wheel drive motor and a rear wheel drive motor.

Abstract: The ceiling fan motor according to the present invention includes a rotor assembly including a rotor housing installed with a plurality of yoke pieces and a plurality of magnets in the inner side, the rotor housing having a plurality of magnet fixing parts formed between the plurality of magnets, a stator assembly placed in the inner side of the rotor assembly, the stator assembly including a stator core, and an upper insulator and a lower insulator engaged with the upper part and lower part of the stator core, and a shaft fixed being engaged with the center part of the stator core, and the magnet is engaged being forcibly press-fitted between the fixing parts.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: The ceiling fan motor according to the present invention includes a rotor assembly including a rotor housing installed with a plurality of yoke pieces and a plurality of magnets in the inner side, the rotor housing having a plurality of magnet fixing parts formed between the plurality of magnets, a stator assembly placed in the inner side of the rotor assembly, the stator assembly including a stator core, and an upper insulator and a lower insulator engaged with the upper part and lower part of the stator core, and a shaft fixed being engaged with the center part of the stator core, and the magnet is engaged being forcibly press-fitted between the fixing parts.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.

Abstract: Disclosed herein is a stator assembly for a motor including: a stator core which includes a rounded base having a plurality of first holes formed in the vertical direction and a plurality of teeth radially formed on the outer circumferential surface of the base; an insulation coating layer formed on the entire surface of the stator core except the inner face of the base and the periphery of the first hole; and one or more connection parts connected to the rounded base.

Abstract: Disclosed herein is a stator assembly for a motor including: a stator core which includes a rounded base having a plurality of first holes formed in the vertical direction and a plurality of teeth radially formed on the outer circumferential surface of the base; an insulation coating layer formed on the entire surface of the stator core except the inner face of the base and the periphery of the first hole; and one or more connection parts connected to the rounded base.

Abstract: Disclosed herein is a system for handling scheduled lending and self-returning of articles to which RFID tags are attached. The system includes a body. The body includes, on a front surface thereof, a display for displaying a method of using the system, handling processes, and processing results, a speaker, a receipt issuing unit, a manipulational information input unit, an external antenna for transmitting/receiving information to/from the RFID tags, and a plurality of article depositories having respective internal antennas for transmitting/receiving information to/from the RFID tags.

Abstract: Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is manipulated through dipole polarization switching of the ferroelectric compound semiconductor without a change in bias. Giant Zeeman splitting properties of the diluted magnetic semiconductor and polarization properties of the ferroelectric compound semiconductor are applied in conjunction with the Pauli exclusion principle, thus enabling the combination or separation of carriers in spin-up and spin-down states in the hybrid double quantum disk structure. The spin relaxation time in the structure is on the order of microseconds, during which the spin state is well-defined, and therefore, the structure can be applied to microprocessors having gigahertz clock speeds.

Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.

Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.

Abstract: Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is manipulated through dipole polarization switching of the ferroelectric compound semiconductor without a change in bias. Giant Zeeman splitting properties of the diluted magnetic semiconductor and polarization properties of the ferroelectric compound semiconductor are applied in conjunction with the Pauli exclusion principle, thus enabling the combination or separation of carriers in spin-up and spin-down states in the hybrid double quantum disk structure. The spin relaxation time in the structure is on the order of microseconds, during which the spin state is well-defined, and therefore, the structure can be applied to microprocessors having gigahertz clock speeds.

Abstract: Disclosed herein is a system for handling scheduled lending and self-returning of articles to which RFID tags are attached. The system includes a body. The body includes, on a front surface thereof, a display for displaying a method of using the system, handling processes, and processing results, a speaker, a receipt issuing unit, a manipulational information input unit, an external antenna for transmitting/receiving information to/from the RFID tags, and a plurality of article depositories having respective internal antennas for transmitting/receiving information to/from the RFID tags.

Abstract: The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film.

Abstract: The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film.