Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: A system-on-chip including: a first slave having a first safety level; a second slave having a second safety level; a first master having a third safety level, the first master outputs a first access request for the first slave and a second access request for the second slave; a safety function protection controller that outputs first attribute information corresponding to the first safety level, second attribute information corresponding to the second safety level, and third attribute information corresponding to the third safety level; and an interconnect bus that receives the first, second and third attribute information, transfers the first access request to the first slave when it is determined that the third safety level is higher than or equal to the first safety level, and blocks the second access request when it is determined that the third safety level is lower than the second safety level.

Abstract: A system-on-chip including: a first slave having a first safety level; a second slave having a second safety level; a first master having a third safety level, the first master outputs a first access request for the first slave and a second access request for the second slave; a safety function protection controller that outputs first attribute information corresponding to the first safety level, second attribute information corresponding to the second safety level, and third attribute information corresponding to the third safety level; and an interconnect bus that receives the first, second and third attribute information, transfers the first access request to the first slave when it is determined that the third safety level is higher than or equal to the first safety level, and blocks the second access request when it is determined that the third safety level is lower than the second safety level.

Abstract: A system-on-chip including: a first slave having a first safety level; a second slave having a second safety level; a first master having a third safety level, the first master outputs a first access request for the first slave and a second access request for the second slave; a safety function protection controller that outputs first attribute information corresponding to the first safety level, second attribute information corresponding to the second safety level, and third attribute information corresponding to the third safety level; and an interconnect bus that receives the first, second and third attribute information, transfers the first access request to the first slave when it is determined that the third safety level is higher than or equal to the first safety level, and blocks the second access request when it is determined that the third safety level is lower than the second safety level.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.

Abstract: A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.

Abstract: A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.