Patents by Inventor Hee Sik Park

Hee Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067065
    Abstract: Provided is a duct docking device for a ventilation seat of a vehicle. The duct docking device enables air to be easily blown to a seatback and a seat cushion with a passenger in a seat using only one blower by enabling a seatback duct mounted at the seatback and a seat cushion duct mounted at the seat cushion to be hermetically docked through a connector duct, etc. at an unfolded position of the seatback in which a passenger can sit, and by enabling the seatback duct mounted at the seatback and the seat cushion duct mounted at the seat cushion to be separated from each other at a folded position of the seatback in consideration of that there is no passenger in the seat.
    Type: Application
    Filed: December 21, 2022
    Publication date: February 29, 2024
    Inventors: Deok Soo Lim, Sang Hark Lee, Sang Soo Lee, Jung Sang You, Sang Do Park, Chan Ho Jung, Gun Chu Park, Gi Tae Jo, Jin Sik Kim, Hee Dong Yoon, Ho Sub Lim, Jae Hyun Park
  • Patent number: 11916241
    Abstract: Disclosed are a method for manufacturing a secondary battery pouch film having at least an outer layer, a metal layer, a primer layer, and a sealant layer, or at least an outer layer, a metal layer, a primer layer, a melt-extrusion resin layer, and a sealant layer in this order, the method including: a drying process of applying and heating a primer layer composition on the metal layer so as to dry the primer layer composition and cure at least a part of the primer layer composition. The organic solvent-based emulsion composition contains acid-modified polypropylene and a curing agent and has a curing start temperature of 150° C. or lower, preferably 135° C. to 150° C., and a drying process temperature of 150° C. or lower, preferably 135° C. to 150° C. The method is not subjected to a thermal lamination process when laminating sealant layer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 27, 2024
    Assignee: Youlchon Chemical Co., Ltd.
    Inventors: Nok Jung Song, Han Chul Park, Hee Sik Han, Ji Min Lee
  • Patent number: 11917907
    Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 27, 2024
    Assignee: Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Kyoung-Jin Park, Tae-Jin Lee, Jae-Hoon Shim, Yoo Jin Doh, Hee-Choon Ahn, Young-Kwang Kim, Doo-Hyeon Moon, Jeong-Eun Yang, Su-Hyun Lee, Chi-Sik Kim, Ji-Song Jun
  • Patent number: 11912915
    Abstract: The present invention relates to a phosphine precursor for the preparation of a quantum dot, and a quantum dot prepared therefrom. Using the phosphine precursor for the preparation of a quantum dot of the present invention, a quantum dot with improved luminous efficiency and higher luminous color purity can be provided.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 27, 2024
    Assignee: SK Chemicals Co., Ltd.
    Inventors: Hee Il Chae, Jeong Ho Park, Kyung Sil Yoon, Ju-Sik Kang, Yu Mi Chang, Nam-Choul Yang, Jae Kyun Park, Song Lee
  • Publication number: 20220383954
    Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.
    Type: Application
    Filed: February 15, 2022
    Publication date: December 1, 2022
    Applicant: SK hynix Inc.
    Inventors: Hyeok Jun CHOI, Hee Sik PARK, Seung Geun JEONG
  • Patent number: 7889557
    Abstract: A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor and the memory cell adjacent to the source selection transistor and between the drain selection transistor and the memory cell adjacent to the drain selection transistor, prevents the memory cell adjacent to the source or drain selection transistor from being degraded in programming speed due to program disturbance.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: February 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee Sik Park, Keon Soo Shim, Jong Soon Leem
  • Publication number: 20090179248
    Abstract: A NAND flash memory device includes a semiconductor substrate having a drain select transistor; a source select transistor, and memory cell transistors connected in series between the drain select transistor and the source select transistor, and an oxide film formed in the semiconductor substrate at each of a first side and a second side of a gate of the source select transistor. A method of manufacturing a NAND flash memory device includes providing the semiconductor substrate and forming the oxide film in the semiconductor substrate at each of the first side and the second side of the gate of the source select transistor.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 16, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hee Sik Park, Seong Jo Park
  • Patent number: 7359239
    Abstract: Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third group of memory cells respectively connected to the remaining word lines other than the first and last word lines. Accordingly, the program speed of the first and second groups of the memory cells can be improved.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: April 15, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Sik Park
  • Publication number: 20080079055
    Abstract: A non-volatile memory device including a semiconductor substrate, an insulating layer, a channel boosting capacitor and a plug. A plurality of memory cells connected in series between a source select line and a drain select line are formed in the semiconductor substrate. The insulating layer is formed on the semiconductor substrate. The channel boosting capacitor is formed on a predetermined region of the insulating layer. A lower electrode, a dielectric layer and an upper electrode are laminated on the channel boosting capacitor. The plug connects one of the lower electrode and the upper electrode of the channel boosting capacitor to the semiconductor substrate between the source select line and memory cells through the insulating layer.
    Type: Application
    Filed: December 7, 2006
    Publication date: April 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Hee Sik Park
  • Patent number: 7310280
    Abstract: A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: December 18, 2007
    Assignee: Hynix Semiconductor Inc
    Inventors: Hee Sik Park, Kyeong Bock Lee, Byung Soo Park