Patents by Inventor Hee-sook Cheon

Hee-sook Cheon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943908
    Abstract: A method of forming a semiconductor device includes forming a mold structure on a substrate, forming a first mask layer having a deposition thickness on the mold structure and patterning the first mask layer to form first mask openings which expose the mold structure. The mold structure is etched to form holes that penetrate the mold structure. The first mask layer is thinned to form mask portions having thickness smaller than the deposition thickness. Conductive patterns are formed to fill the holes and the first mask openings. The first mask layer including the mask portions is etched to expose the mold structure. The conductive patterns include protrusions. A chemical mechanical polishing process is performed to remove the protrusions of the conductive patterns.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Woo Bae, Su Young Shin, Young Ho Koh, Bo Un Yoon, Il Young Yoon, Yang Hee Lee, Hee Sook Cheon
  • Patent number: 10711160
    Abstract: A slurry composition for polishing a metal layer and a method for fabricating a semiconductor device using the same are provided. The slurry composition for polishing a metal layer includes polishing particles including a metal oxide, an oxidizer including hydrogen peroxide, and a first polishing regulator including at least one selected from a group consisting of phosphate, phosphite, hypophosphite, and metaphosphate, wherein a content of the oxidizer is 0.01 wt % to 0.09 wt % with respect to 100 wt % of the slurry composition for polishing the metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 14, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KCTECH Co., Ltd.
    Inventors: Seung Ho Park, Hyun Goo Kong, Jung Hun Kim, Sang Mi Lee, Woo In Lee, Hee Sook Cheon, Sang Kyun Kim, Hao Cui, Jong Hyuk Park, Il Young Yoon
  • Publication number: 20200098763
    Abstract: A method of forming a semiconductor device includes forming a mold structure on a substrate, forming a first mask layer having a deposition thickness on the mold structure and patterning the first mask layer to form first mask openings which expose the mold structure. The mold structure is etched to form holes that penetrate the mold structure. The first mask layer is thinned to form mask portions having thickness smaller than the deposition thickness. Conductive patterns are formed to fill the holes and the first mask openings. The first mask layer including the mask portions is etched to expose the mold structure. The conductive patterns include protrusions. A chemical mechanical polishing process is performed to remove the protrusions of the conductive patterns.
    Type: Application
    Filed: May 14, 2019
    Publication date: March 26, 2020
    Inventors: JIN WOO BAE, Su Young SHIN, Young Ho KOH, Bo Un YOON, II Young YOON, Yang Hee LEE, Hee Sook CHEON
  • Publication number: 20190341358
    Abstract: A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern.
    Type: Application
    Filed: January 21, 2019
    Publication date: November 7, 2019
    Inventors: YANG HEE LEE, Jong Hyuk Park, Jin Woo Bae, Choong Seob Shin, Hyo Jin Oh, Bo Un Yoon, Il Young Yoon, Hee Sook Cheon
  • Publication number: 20180355213
    Abstract: A slurry composition for polishing a metal layer and a method for fabricating a semiconductor device using the same are provided. The slurry composition for polishing a metal layer includes polishing particles including a metal oxide, an oxidizer including hydrogen peroxide, and a first polishing regulator including at least one selected from a group consisting of phosphate, phosphite, hypophosphite, and metaphosphate, wherein a content of the oxidizer is 0.01 wt % to 0.09 wt % with respect to 100 wt % of the slurry composition for polishing the metal layer.
    Type: Application
    Filed: January 30, 2018
    Publication date: December 13, 2018
    Inventors: Seung Ho Park, Hyun Goo KONG, Jung Hun KIM, Sang Mi LEE, Woo In LEE, Hee Sook CHEON, Sang Kyun KIM, Hao CUI, Jong Hyuk PARK, Il Young YOON
  • Publication number: 20160079260
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.
    Type: Application
    Filed: June 3, 2015
    Publication date: March 17, 2016
    Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
  • Patent number: 9269720
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang