Abstract: A gate driver for a display device and a display device including the same are disclosed. In one aspect, the gate driver includes first through N-th scan drivers configured to respectively output first through N-th scan signals, where N is an integer greater than 1. The gate driver also includes first through N-th sensing drivers configured to respectively output first through N-th sensing signals, wherein an M-th one of the first through N-th sensing drivers is configured to activate an M-th one of the first through N-th sensing signals K times during an active period of an (M+1)-th one of the first through N-th scan signals, where M is an integer greater than 0 and less than N and K is an integer greater than 1.

Abstract: An organic light emitting display device includes pixels positioned at crossing regions between data lines and scan lines, each of the pixels including an organic light emitting diode, a scan driver configured to supply a scan signal to scan lines, a data driver configured to drive the data lines, wherein the data driver includes, in each channel, a supply part comprising a digital-to-analog converter configured to generate data signals using second data supplied from outside in a driving period, and a deterioration part configured to measure deterioration information of the organic light emitting diode using the digital-to-analog converter in a sensing period.

Abstract: An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal.

Abstract: A noise-removing circuit includes a first capacitor to charge a first voltage supplied to a first node during a first period in which a first switching control signal is supplied, a second capacitor to charge a second voltage supplied to a third node during the first period, a third capacitor to charge the first voltage during a second period in which a second switching control signal is supplied, and to charge the second voltage charged in the second capacitor as a third voltage during a third period in which a third switching control signal is supplied, a fourth capacitor to charge the second voltage during the second period, and to charge the first voltage charged in the first capacitor as a fourth voltage during the third period, and a differential amplifier to output a voltage difference between the third voltage and the fourth voltage.

Abstract: An error compensator and an organic light emitting display device using the same. The organic light emitting display device includes pixels each having a driving transistor and an organic light emitting diode; and a sensing unit extracting at least one of a first information including the threshold voltage of the driving transistor or a second information including the degradation of the organic light emitting diode from a pixel of the pixels. In the organic light emitting display device, the sensing unit includes an amplifier amplifying a voltage corresponding to the at least one of the first information or the second information; and an error compensator compensating for error components of elements included in the amplifier and the error compensator.

Abstract: A gate driver for a display device and a display device including the same are disclosed. In one aspect, the gate driver includes first through N-th scan drivers configured to respectively output first through N-th scan signals, where N is an integer greater than 1. The gate driver also includes first through N-th sensing drivers configured to respectively output first through N-th sensing signals, wherein an M-th one of the first through N-th sensing drivers is configured to activate an M-th one of the first through N-th sensing signals K times during an active period of an (M+1)-th one of the first through N-th scan signals, where M is an integer greater than 0 and less than N and K is an integer greater than 1.

Abstract: A current generating circuit includes a reference voltage generating unit, a clock signal generating unit, a reference current generating unit, and a current mirror unit. The reference voltage generating unit generates a first reference voltage and a second reference voltage. The clock signal generating unit generates clock signals. The reference current generating unit generates a reference current corresponding to a selection signal based on the first reference voltage. The current mirror unit supplies a first current and a second current based on the reference current. A capacitor charges voltage based on the second current. A selection signal generating unit counts clock signals during a period in which a voltage charged in the capacitor is less than the second reference voltage, and outputs the selection signal based on the counted result.

Abstract: A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled to first and second nodes, and ground. The first capacitor is coupled between the second node and ground. The second capacitor is coupled between a third node and ground. The first unit couples a current source to the first node during a first period and an output line to the first node during a second period. The second unit couples the first node to the second node during the first period. The third unit couples the first terminal to the second node and couples the second and third terminals to the third node during the first period, and couples the first terminal to the third node and couples the second and third terminals to the second node during the second period.

Abstract: A noise-removing circuit includes a first capacitor to charge a first voltage supplied to a first node during a first period in which a first switching control signal is supplied, a second capacitor to charge a second voltage supplied to a third node during the first period, a third capacitor to charge the first voltage during a second period in which a second switching control signal is supplied, and to charge the second voltage charged in the second capacitor as a third voltage during a third period in which a third switching control signal is supplied, a fourth capacitor to charge the second voltage during the second period, and to charge the first voltage charged in the first capacitor as a fourth voltage during the third period, and a differential amplifier to output a voltage difference between the third voltage and the fourth voltage.

Abstract: A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled to first and second nodes, and ground. The first capacitor is coupled between the second node and ground. The second capacitor is coupled between a third node and ground. The first unit couples a current source to the first node during a first period and an output line to the first node during a second period. The second unit couples the first node to the second node during the first period. The third unit couples the first terminal to the second node and couples the second and third terminals to the third node during the first period, and couples the first terminal to the third node and couples the second and third terminals to the second node during the second period.

Abstract: A current generating circuit includes a reference voltage generating unit, a clock signal generating unit, a reference current generating unit, and a current mirror unit. The reference voltage generating unit generates a first reference voltage and a second reference voltage. The clock signal generating unit generates clock signals. The reference current generating unit generates a reference current corresponding to a selection signal based on the first reference voltage. The current mirror unit supplies a first current and a second current based on the reference current. A capacitor charges voltage based on the second current. A selection signal generating unit counts clock signals during a period in which a voltage charged in the capacitor is less than the second reference voltage, and outputs the selection signal based on the counted result.

Abstract: An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal.

Abstract: An organic light emitting display device includes pixels positioned at crossing regions between data lines and scan lines, each of the pixels including an organic light emitting diode, a scan driver configured to supply a scan signal to scan lines, a data driver configured to drive the data lines, wherein the data driver includes, in each channel, a supply part comprising a digital-to-analog converter configured to generate data signals using second data supplied from outside in a driving period, and a deterioration part configured to measure deterioration information of the organic light emitting diode using the digital-to-analog converter in a sensing period.

Abstract: An error compensator and an organic light emitting display device using the same. The organic light emitting display device includes pixels each having a driving transistor and an organic light emitting diode; and a sensing unit extracting at least one of a first information including the threshold voltage of the driving transistor or a second information including the degradation of the organic light emitting diode from a pixel of the pixels. In the organic light emitting display device, the sensing unit includes an amplifier amplifying a voltage corresponding to the at least one of the first information or the second information; and an error compensator compensating for error components of elements included in the amplifier and the error compensator.