Abstract: A memory system includes a non-volatile memory device and controller circuitry. The non-volatile memory device includes an array of memory cells that includes memory blocks and pages. Each separate memory block includes a separate, respective set of one or more pages. The controller circuitry is configured to control an operation of the non-volatile memory device. The controller circuitry includes processing circuitry configured to perform a recovery operation for the non-volatile memory device in response to a determination that a specific event has occurred at the memory system during a program operation of the non-volatile memory device. The recovery operation includes determining status information associated with a first group including at least one page, determining a quantity of a set of pages included in a second group based on the status information, and programming dummy data for one or more pages of the set of pages included in the second group.

Abstract: A memory system includes a non-volatile memory device and controller circuitry. The non-volatile memory device includes an array of memory cells that includes memory blocks and pages. Each separate memory block includes a separate, respective set of one or more pages. The controller circuitry is configured to control an operation of the non-volatile memory device. The controller circuitry includes processing circuitry configured to perform a recovery operation for the non-volatile memory device in response to a determination that a specific event has occurred at the memory system during a program operation of the non-volatile memory device. The recovery operation includes determining status information associated with a first group including at least one page, determining a quantity of a set of pages included in a second group based on the status information, and programming dummy data for one or more pages of the set of pages included in the second group.

Abstract: A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

Abstract: A memory device includes a nonvolatile memory having a first block and a memory controller configured to exchange data with the nonvolatile memory. The memory controller includes a first processor to divide the first block into first and second domains, a second processor to generate a reclaim signal by determining whether to perform reclaiming on each of the first and second domains and a third processor performer which reclaims each of the first and second domains according to the reclaim signal and merges the first and second domains.

Abstract: According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of planes and each plane includes a plurality of memory blocks. The memory controller is configured to classify the memory blocks of each of the planes into a plurality of groups. The memory controller is configured to select at least two memory blocks in a corresponding one of the groups, and to control the nonvolatile memory device so that the selected at least two memory blocks are multi-block erased.

Abstract: A method managing execution of recovery code in a memory system includes; upon detecting a read error using a CPU and firmware to execute recovery code defining a read recovery operation including a read retry operation, during execution of the recovery code, generating a read request directed to the read retry operation, and immediately thereafter terminating execution of the recovery code, and thereafter, only upon receiving an asynchronous interrupt from the memory controller following completion of the read retry operation, the CPU resumes execution of the recovery code by the firmware, otherwise the CPU performs another task unrelated to execution of the recovery code.

Abstract: A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word line adjacent to the first word line, and performing a recharge program operation on the memory cells connected to the first word line.

Abstract: According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of planes and each plane includes a plurality of memory blocks. The memory controller is configured to classify the memory blocks of each of the planes into a plurality of groups. The memory controller is configured to select at least two memory blocks in a corresponding one of the groups, and to control the nonvolatile memory device so that the selected at least two memory blocks are multi-block erased.

Abstract: A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word line adjacent to the first word line, and performing a recharge program operation on the memory cells connected to the first word line.

Abstract: A method managing execution of recovery code in a memory system includes; upon detecting a read error using a CPU and firmware to execute recovery code defining a read recovery operation including a read retry operation, during execution of the recovery code, generating a read request directed to the read retry operation, and immediately thereafter terminating execution of the recovery code, and thereafter, only upon receiving an asynchronous interrupt from the memory controller following completion of the read retry operation, the CPU resumes execution of the recovery code by the firmware, otherwise the CPU performs another task unrelated to execution of the recovery code.