Abstract: A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.

Abstract: A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.

Abstract: Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.

Abstract: Fine resolution pulse width modulation is achieved through feed-forward edge extending logic. A ring-oscillator produces phase-shifted versions of a system clock and two latches operate in parallel with the system clock output from the multiplexer clocking a first latch and a selected phase-shifted version of the system clock from the multiplexer clocking the second latch. The first latch receives a coarse output pulse equal to a selected number of clock periods as an input, while the second latch receives the output of the first latch as an input. A logic gate combines outputs from the latches to produce the output pulse having a trailing edge extended by a selected number of phase divisions.

Abstract: Testing of a wireless transceiver employs a selectively activated multi-subcarrier test vector or corresponding waveform for which all subcarriers are activated except subcarriers below a selected subcarrier fundamental and harmonics of the selected subcarrier fundamental. Use of selectively activated multi-subcarrier testing allows measurement of inter-modulation distortion, harmonic distortion, frequency response, and phase noise using a common spectrum analyzer, with individual results pinpointing sources of impairment.

Abstract: There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the se

Abstract: Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.

Abstract: A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value based on the magnitude of a previous error value for a previous loop iteration, plus margins conversion housekeeping and the step size of the next loop iteration. At a timing prior to a filter reading the error value that equals the number of clock cycles set by the predictor, a timing unit triggers the analog-to-digital conversion, reducing loop latency and improving performance.

Abstract: Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase select signals from the digital pulse width modulator and the dithering signal to the leading and trailing edge control signals, with the output employed by multiplexers as select controls in selecting a phase of from the phase-shifted versions of the system clock with which to clock latches controlling the leading and trailing edges.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency of LO, wherein the RF mixer generates a first intermediate frequency (IF) signal having a frequency of IF; 2) a frequency divider circuit capable of receiving the first LO signal having the frequency of LO and generating therefrom a second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and 3) an intermediate frequency (IF) mixer having a first input port capable of receiving the first IF signal and a second input port capable of receiving the second LO signal having the frequency of LO/N, and wherein the IF mixer generates a baseband output signal.

Abstract: Rejection of local oscillator alias response is provided in a mixing circuit by (1) a switching mixer producing an output that changes at least twice between two states (e.g., high-low-high or low-high-low) during each local oscillator period, and (2) a charge integrator integrating current output from the switching mixer over the local oscillator period. The switching mixer and charge integrator produce a sampled data format, double sideband signal with serial cancellation of the switching mixer's alias responses. An extension unit connected in series with the switching mixer and charge integrator, and implementing a transform function computing a difference between consecutive samples, produces a cascading effect with the switching mixer and charge integrator, optionally producing additional nulls suppressing alias response at frequencies near the local oscillator frequency.

Abstract: Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator signal controlling the switching mixer. An aperture or duty cycle of the gate clock signal determines which harmonic is rejected or suppressed, which is preferably a third and/or fifth harmonic since response of the balanced differential switching mixer to even harmonics is negligible. The resulting simple, efficient circuit is readily integrated directly into a phase-alternating mixer structure for a chopper-direct-conversion radio.

Abstract: A phase alternating mixer is implemented by common-base differential transistor pairs, with two cross-coupled pairs providing a switching mixer function with harmonic gating suppression of harmonic responses to the switching mixing by control of local oscillator signals controlling switching of the differential transistor pairs. Rather than a resistive load, a switched capacitance load and integrating capacitors are connected to the output of the differential transistor pairs to provide first order low pass filtering of the double sideband output from the differential pairs, with a controlled bandwidth. Channel select switches demultiplex the double sideband signal into a baseband signal.

Abstract: An analog-to-digital converter error detector suitable for single-chip control loop applications employs a single comparator determining the difference between an initial input voltage and a reference voltage in one or more conversion iterations, with the difference reduced in nonlinear steps during each conversion iteration based on the ratio between sampling and discharge capacitances. The number of conversion iterations required to reduce the initial input voltage to below the reference voltage is counted as representing the difference, with output codes representing the conversion iteration count having a step size increasing with the count value and selected to reduce downstream processing.

Abstract: Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.

Abstract: A radio frequency (RF) receiver comprising: 1) a local oscillator (LO) circuit capable of receiving a local oscillator (LO) reference signal having frequency, LO, and a double sideband (DSB) clock signal having a frequency, DSB, and generating therefrom an in-phase product signal of the LO reference signal and the DSB clock signal in which a polarity of the LO reference signal is reversed at the DSB frequency of the DSB clock signal; and 2) a first radio frequency (RF) mixer having a first input port capable of receiving the in-phase product signal from the LO circuit and a second input port capable of receiving a modulated radio frequency (RF) signal, wherein the first RF mixer generates a first downconverted output signal.

Abstract: An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.

Abstract: A chopper-direct-conversion (CDC) radio receiver includes a phase-alternating mixer receiving an antenna input signal and at least one local oscillator signal and generating a double sideband signal in a single mixing step. The phase-alternating mixer may be implemented by two parallel mixers each mixing the input signal with one of two local oscillator signals and an adder receiving and summing outputs from the two parallel mixers, by a track-and-hold circuit sampling the input signal based upon the local oscillator signal, or by a window averaging circuit averaging the input signal across a period of the local oscillator signal. The CDC architecture is suitable for fabrication on a single chip and offers solutions to virtually all problems found in conventional direct-conversion receivers.

Abstract: A radio frequency (RF) demodulation circuit comprising a harmonic rejection mixing stage capable of receiving and mixing an incoming radio frequency (RF) signal having a frequency RF and a reference local oscillator (LO) signal having a frequency LO and generating an output signal in which out-of-band harmonic signals are suppressed. The harmonic rejection mixing stage comprises 1) a multiphase local oscillator (LO) generator for receiving the reference LO signal and generating M phase-shifted local oscillator signals having frequencies LO and 2) M mixers, each of the M mixers receiving the incoming radio frequency signal and one of the M phase-shifted local oscillator signals. Each of the M mixers generates a subcomponent signal. The subcomponent signals are then scaled and combined to produce the output signal.